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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2017-01-10 17:24:01 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2017-07-04 09:22:20 +0200 |
| commit | 3e92250589c617b8cff74cbe6641ba2459717a27 (patch) | |
| tree | 47ad4f6dfb515526dc266cb87195490e91f3c371 | |
| parent | 79549c996056ce1ad820061622e71d4a0444d3c7 (diff) | |
| download | qemu-3e92250589c617b8cff74cbe6641ba2459717a27.zip qemu-3e92250589c617b8cff74cbe6641ba2459717a27.tar.gz qemu-3e92250589c617b8cff74cbe6641ba2459717a27.tar.bz2 | |
target-microblaze: Don't hard code 0xb as initial MB version
Don't hard code 0xb as initial MB version.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| -rw-r--r-- | target/microblaze/cpu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index af70faa..4bc77df 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -152,8 +152,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ | PVR0_USE_ICACHE_MASK \ - | PVR0_USE_DCACHE_MASK \ - | (0xb << 8); + | PVR0_USE_DCACHE_MASK; env->pvr.regs[2] = PVR2_D_OPB_MASK \ | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ |