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| author | Petar Jovanovic <petarj@mips.com> | 2012-11-26 16:13:21 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-12-06 08:10:50 +0100 |
| commit | 34f5606ee101f82a247d09d05644ad2a63c8e342 (patch) | |
| tree | a7416f9afd7031e08289476bdcbcbaadb8ad318e | |
| parent | 80625b97b52836b944a6438e8e3e9d992e6a00b6 (diff) | |
| download | qemu-34f5606ee101f82a247d09d05644ad2a63c8e342.zip qemu-34f5606ee101f82a247d09d05644ad2a63c8e342.tar.gz qemu-34f5606ee101f82a247d09d05644ad2a63c8e342.tar.bz2 | |
target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask.
This change contains both fix for the instruction and to the existing test.
Signed-off-by: Petar Jovanovic <petarj@mips.com>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-mips/dsp_helper.c | 2 | ||||
| -rw-r--r-- | tests/tcg/mips/mips32-dsp/insv.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index e7949c2..fda5f04 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ \ filter = ((int32_t)0x01 << size) - 1; \ filter = filter << pos; \ - temprs = rs & filter; \ + temprs = (rs << pos) & filter; \ temprt = rt & ~filter; \ temp = temprs | temprt; \ \ diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c index 7e3b047..243b007 100644 --- a/tests/tcg/mips/mips32-dsp/insv.c +++ b/tests/tcg/mips/mips32-dsp/insv.c @@ -10,7 +10,7 @@ int main() dsp = 0x305; rt = 0x12345678; rs = 0x87654321; - result = 0x12345338; + result = 0x12345438; __asm ("wrdsp %2, 0x03\n\t" "insv %0, %1\n\t" |