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| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-13 01:39:17 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-13 11:35:55 +0100 |
| commit | 30724e758a21ba9f807efafe268626bd479db9de (patch) | |
| tree | b56a3451ad94b9dc2c7446c0de68a5d0ad400687 | |
| parent | 65850a0254744050f79c42347f84cc79d0c2348e (diff) | |
| download | qemu-30724e758a21ba9f807efafe268626bd479db9de.zip qemu-30724e758a21ba9f807efafe268626bd479db9de.tar.gz qemu-30724e758a21ba9f807efafe268626bd479db9de.tar.bz2 | |
target-mips: update address space definitions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-mips/mips-defs.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 0f6a956..c57de02 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -8,14 +8,14 @@ #define TARGET_PAGE_BITS 12 #define MIPS_TLB_MAX 128 -/* ??? MIPS64 no doubt has a larger address space. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #if defined(TARGET_MIPS64) #define TARGET_LONG_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 36 +#define TARGET_VIRT_ADDR_SPACE_BITS 42 #else #define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 36 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif /* Masks used to mark instructions to indicate which ISA level they |