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| author | David Hildenbrand <david@redhat.com> | 2019-03-07 13:15:25 +0100 |
|---|---|---|
| committer | Cornelia Huck <cohuck@redhat.com> | 2019-03-11 09:31:01 +0100 |
| commit | 2ff47e6cce21c7a210d99f018d10a94404e797e9 (patch) | |
| tree | c450a64d00a41641f1c58eefc6823e517fc54537 | |
| parent | f6c7ff67574d1dd7266e6a0e16db5e891b3a4444 (diff) | |
| download | qemu-2ff47e6cce21c7a210d99f018d10a94404e797e9.zip qemu-2ff47e6cce21c7a210d99f018d10a94404e797e9.tar.gz qemu-2ff47e6cce21c7a210d99f018d10a94404e797e9.tar.bz2 | |
s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
We cannot use gvec expansion as source and destination elements are
have different element numbers. So we'll expand using a fancy loop.
Also, we have to take care of overlapping source and destination
registers, therefore use a safe evaluation irder depending on the
operation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190307121539.12842-19-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| -rw-r--r-- | target/s390x/insn-data.def | 4 | ||||
| -rw-r--r-- | target/s390x/translate_vx.inc.c | 42 |
2 files changed, 46 insertions, 0 deletions
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 3c0b14b..f7232f8 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1010,6 +1010,10 @@ F(0xe762, VLVGP, VRR_f, V, r2, r3, 0, 0, vlvgp, 0, IF_VEC) /* VECTOR LOAD WITH LENGTH */ F(0xe737, VLL, VRS_b, V, la2, r3_32u, 0, 0, vll, 0, IF_VEC) +/* VECTOR MERGE HIGH */ + F(0xe761, VMRH, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC) +/* VECTOR MERGE LOW */ + F(0xe760, VMRL, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index b8e6985..9c2cf8a 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -532,3 +532,45 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *o) tcg_temp_free_ptr(a0); return DISAS_NEXT; } + +static DisasJumpType op_vmr(DisasContext *s, DisasOps *o) +{ + const uint8_t v1 = get_field(s->fields, v1); + const uint8_t v2 = get_field(s->fields, v2); + const uint8_t v3 = get_field(s->fields, v3); + const uint8_t es = get_field(s->fields, m4); + int dst_idx, src_idx; + TCGv_i64 tmp; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + if (s->fields->op2 == 0x61) { + /* iterate backwards to avoid overwriting data we might need later */ + for (dst_idx = NUM_VEC_ELEMENTS(es) - 1; dst_idx >= 0; dst_idx--) { + src_idx = dst_idx / 2; + if (dst_idx % 2 == 0) { + read_vec_element_i64(tmp, v2, src_idx, es); + } else { + read_vec_element_i64(tmp, v3, src_idx, es); + } + write_vec_element_i64(tmp, v1, dst_idx, es); + } + } else { + /* iterate forward to avoid overwriting data we might need later */ + for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(es); dst_idx++) { + src_idx = (dst_idx + NUM_VEC_ELEMENTS(es)) / 2; + if (dst_idx % 2 == 0) { + read_vec_element_i64(tmp, v2, src_idx, es); + } else { + read_vec_element_i64(tmp, v3, src_idx, es); + } + write_vec_element_i64(tmp, v1, dst_idx, es); + } + } + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} |