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| author | Aurelien Jarno <aurelien@aurel32.net> | 2015-07-30 23:39:34 +0200 |
|---|---|---|
| committer | Michael Roth <mdroth@linux.vnet.ibm.com> | 2015-08-04 12:30:20 -0500 |
| commit | f9c0ae272389b3581be13fe13986d7c509995be1 (patch) | |
| tree | 8f9a3b01a81ba82b6f3d5cb235019360fc10f0df | |
| parent | c8bd74d1d509df5dd1afc6b79413f148f2889692 (diff) | |
| download | qemu-f9c0ae272389b3581be13fe13986d7c509995be1.zip qemu-f9c0ae272389b3581be13fe13986d7c509995be1.tar.gz qemu-f9c0ae272389b3581be13fe13986d7c509995be1.tar.bz2 | |
tcg/mips: fix TLB loading for BE host with 32-bit guests
For 32-bit guest, we load a 32-bit address from the TLB, so there is no
need to compensate for the low or high part. This fixes 32-bit guests on
big-endian hosts.
Cc: qemu-stable@nongnu.org
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit e72c4fb81db52be881c9356f1c60e0a7817d2d32)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| -rw-r--r-- | tcg/mips/tcg-target.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 5414b83..6ca35a7 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -963,9 +963,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, } /* Load the tlb comparator. */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF); if (TARGET_LONG_BITS == 64) { + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF); tcg_out_opc_imm(s, OPC_LW, base, TCG_REG_A0, cmp_off + HI_OFF); + } else { + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off); } /* Mask the page bits, keeping the alignment bits to compare against. |