diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-02-19 23:52:06 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2013-02-23 17:25:29 +0000 |
| commit | c9f10124a2704b6bab21b31e79735b18d414a654 (patch) | |
| tree | ef1c829e8c9a78295923de916610620bb4359bf5 | |
| parent | 831d7fe800774db0d7142fdf2a8f8758c8bf9c92 (diff) | |
| download | qemu-c9f10124a2704b6bab21b31e79735b18d414a654.zip qemu-c9f10124a2704b6bab21b31e79735b18d414a654.tar.gz qemu-c9f10124a2704b6bab21b31e79735b18d414a654.tar.bz2 | |
target-arm: Use mul[us]2 and add2 in umlal et al
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
| -rw-r--r-- | target-arm/helper.c | 5 | ||||
| -rw-r--r-- | target-arm/helper.h | 2 | ||||
| -rw-r--r-- | target-arm/translate.c | 26 |
3 files changed, 14 insertions, 19 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index e63da57..e97e1a5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2893,11 +2893,6 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) return (a & mask) | (b & ~mask); } -uint32_t HELPER(logicq_cc)(uint64_t val) -{ - return (val >> 32) | (val != 0); -} - /* VFP support. We follow the convention used for VFP instructions: Single precision routines have a "s" suffix, double precision a "d" suffix. */ diff --git a/target-arm/helper.h b/target-arm/helper.h index 8544f82..bca5a5b 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -46,8 +46,6 @@ DEF_HELPER_3(usat16, i32, env, i32, i32) DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_1(logicq_cc, i32, i64) - DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception, void, env, i32) diff --git a/target-arm/translate.c b/target-arm/translate.c index 129f674..efe76d0 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6433,13 +6433,11 @@ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) tcg_temp_free_i64(tmp); } -/* Set N and Z flags from a 64-bit value. */ -static void gen_logicq_cc(TCGv_i64 val) +/* Set N and Z flags from hi|lo. */ +static void gen_logicq_cc(TCGv lo, TCGv hi) { - TCGv tmp = tcg_temp_new_i32(); - gen_helper_logicq_cc(tmp, val); - gen_logic_CC(tmp); - tcg_temp_free_i32(tmp); + tcg_gen_mov_i32(cpu_NF, hi); + tcg_gen_or_i32(cpu_ZF, lo, hi); } /* Load/Store exclusive instructions are implemented by remembering @@ -7219,18 +7217,22 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = load_reg(s, rs); tmp2 = load_reg(s, rm); if (insn & (1 << 22)) { - tmp64 = gen_muls_i64_i32(tmp, tmp2); + tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); } else { - tmp64 = gen_mulu_i64_i32(tmp, tmp2); + tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); } if (insn & (1 << 21)) { /* mult accumulate */ - gen_addq(s, tmp64, rn, rd); + TCGv al = load_reg(s, rn); + TCGv ah = load_reg(s, rd); + tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); + tcg_temp_free(al); + tcg_temp_free(ah); } if (insn & (1 << 20)) { - gen_logicq_cc(tmp64); + gen_logicq_cc(tmp, tmp2); } - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); + store_reg(s, rn, tmp); + store_reg(s, rd, tmp2); break; default: goto illegal_op; |