diff options
author | Richard Henderson <rth@twiddle.net> | 2012-09-24 14:55:47 -0700 |
---|---|---|
committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-09-27 21:38:50 +0200 |
commit | fdefe51c288866b98e62663fa18c8af1d66bf5f6 (patch) | |
tree | 5560732a1024bda244f79a515e6097ae87ffc9d1 | |
parent | 6673f47da21718d07346b0f3725f0dbf0d6d8e45 (diff) | |
download | qemu-fdefe51c288866b98e62663fa18c8af1d66bf5f6.zip qemu-fdefe51c288866b98e62663fa18c8af1d66bf5f6.tar.gz qemu-fdefe51c288866b98e62663fa18c8af1d66bf5f6.tar.bz2 |
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r-- | target-alpha/translate.c | 2 | ||||
-rw-r--r-- | target-arm/translate.c | 2 | ||||
-rw-r--r-- | target-cris/translate.c | 3 | ||||
-rw-r--r-- | target-i386/translate.c | 3 | ||||
-rw-r--r-- | target-lm32/translate.c | 2 | ||||
-rw-r--r-- | target-microblaze/translate.c | 3 | ||||
-rw-r--r-- | target-mips/translate.c | 3 | ||||
-rw-r--r-- | target-openrisc/translate.c | 2 | ||||
-rw-r--r-- | target-ppc/translate.c | 3 | ||||
-rw-r--r-- | target-sh4/translate.c | 2 | ||||
-rw-r--r-- | target-sparc/translate.c | 3 | ||||
-rw-r--r-- | target-xtensa/translate.c | 2 |
12 files changed, 18 insertions, 12 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 3f9aee1..f707d8d 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3421,7 +3421,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, insn = cpu_ldl_code(env, ctx.pc); num_insns++; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(ctx.pc); } diff --git a/target-arm/translate.c b/target-arm/translate.c index f4b447a..5fded49 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9816,7 +9816,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(dc->pc); } diff --git a/target-cris/translate.c b/target-cris/translate.c index 19144b5..755de65 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3074,8 +3074,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) int insn_len = 2; int i; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(dc->pc); + } /* Load a halfword onto the instruction register. */ dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); diff --git a/target-i386/translate.c b/target-i386/translate.c index eb0cabc..323869d 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4202,8 +4202,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) target_ulong next_eip, tval; int rex_w, rex_r; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(pc_start); + } s->pc = pc_start; prefixes = 0; aflag = s->code32; diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 5f6dcba..77c2866 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -942,7 +942,7 @@ static const DecoderInfo decinfo[] = { static inline void decode(DisasContext *dc, uint32_t ir) { - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(dc->pc); } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 9c7d77f..7d864b1 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1664,8 +1664,9 @@ static inline void decode(DisasContext *dc, uint32_t ir) { int i; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(dc->pc); + } dc->ir = ir; LOG_DIS("%8.8x\t", dc->ir); diff --git a/target-mips/translate.c b/target-mips/translate.c index fa79d49..454e5cc 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12124,8 +12124,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) gen_set_label(l1); } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(ctx->pc); + } op = MASK_OP_MAJOR(ctx->opcode); rs = (ctx->opcode >> 21) & 0x1f; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 325ba09..e2cad3a 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1715,7 +1715,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, gen_opc_icount[k] = num_insns; } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(dc->pc); } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ac915cc..1042268 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9690,8 +9690,9 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), little_endian ? "little" : "big"); - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(ctx.nip); + } ctx.nip += 4; table = env->opcodes; num_insns++; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 0fa83ca..9d955eb 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1924,7 +1924,7 @@ static void decode_opc(DisasContext * ctx) { uint32_t old_flags = ctx->flags; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(ctx->pc); } diff --git a/target-sparc/translate.c b/target-sparc/translate.c index b95f91c..e5ebedf 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2394,8 +2394,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; target_long simm; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(dc->pc); + } opc = GET_FIELD(insn, 0, 1); diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index ba3ffcb..b9acd70 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2923,7 +2923,7 @@ static void gen_intermediate_code_internal( gen_opc_icount[lj] = insn_count; } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(dc.pc); } |