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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2018-01-16 13:28:15 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-01-16 13:28:15 +0000 |
| commit | f82a0f449b2fdf314900116047ea6d9ee5a2da06 (patch) | |
| tree | 38d9771b00b1d31fda83ecf471e2f9dc7787f1b5 | |
| parent | 8081796a75414f9ed5ec3d97158e543ed45908ec (diff) | |
| download | qemu-f82a0f449b2fdf314900116047ea6d9ee5a2da06.zip qemu-f82a0f449b2fdf314900116047ea6d9ee5a2da06.tar.gz qemu-f82a0f449b2fdf314900116047ea6d9ee5a2da06.tar.bz2 | |
sdhci: clean up includes
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20180115182436.2066-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/sd/sdhci-internal.h | 4 | ||||
| -rw-r--r-- | hw/sd/sdhci.c | 1 | ||||
| -rw-r--r-- | include/hw/sd/sdhci.h | 7 |
3 files changed, 7 insertions, 5 deletions
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 161177c..248fd02 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -24,8 +24,6 @@ #ifndef SDHCI_INTERNAL_H #define SDHCI_INTERNAL_H -#include "hw/sd/sdhci.h" - /* R/W SDMA System Address register 0x0 */ #define SDHC_SYSAD 0x00 @@ -227,6 +225,4 @@ enum { sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */ }; -extern const VMStateDescription sdhci_vmstate; - #endif diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index b064a08..b7d2a20 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -29,6 +29,7 @@ #include "sysemu/dma.h" #include "qemu/timer.h" #include "qemu/bitops.h" +#include "hw/sd/sdhci.h" #include "sdhci-internal.h" #include "qemu/log.h" diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 0f0c3f1..1335373 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -26,17 +26,19 @@ #define SDHCI_H #include "qemu-common.h" -#include "hw/block/block.h" #include "hw/pci/pci.h" #include "hw/sysbus.h" #include "hw/sd/sd.h" /* SD/MMC host controller state */ typedef struct SDHCIState { + /*< private >*/ union { PCIDevice pcidev; SysBusDevice busdev; }; + + /*< public >*/ SDBus sdbus; MemoryRegion iomem; @@ -46,6 +48,7 @@ typedef struct SDHCIState { qemu_irq ro_cb; qemu_irq irq; + /* Registers cleared on reset */ uint32_t sdmasysad; /* SDMA System Address register */ uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */ uint16_t blkcnt; /* Blocks count for current transfer */ @@ -70,8 +73,10 @@ typedef struct SDHCIState { uint16_t acmd12errsts; /* Auto CMD12 error status register */ uint64_t admasysaddr; /* ADMA System Address Register */ + /* Read-only registers */ uint32_t capareg; /* Capabilities Register */ uint32_t maxcurr; /* Maximum Current Capabilities Register */ + uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ uint32_t buf_maxsz; uint16_t data_count; /* current element in FIFO buffer */ |