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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-28 12:35:05 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-28 12:35:05 +0000 |
| commit | ea4b07f7623c3863d86aad3d5718c28d39e1a1a9 (patch) | |
| tree | f0aa89f6d31cd5c7d6f3138d61acc1399c0c1b93 | |
| parent | 4c2485de385c52cbf3cba1bba37c49b99a47e58c (diff) | |
| download | qemu-ea4b07f7623c3863d86aad3d5718c28d39e1a1a9.zip qemu-ea4b07f7623c3863d86aad3d5718c28d39e1a1a9.tar.gz qemu-ea4b07f7623c3863d86aad3d5718c28d39e1a1a9.tar.bz2 | |
Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3865 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-mips/translate_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 57666d4..72788e8 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -403,9 +403,9 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x36FBFFFF, - .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) | - (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | - (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, /* The architectural limit is 59, but we have hardcoded 36 bit in some places... |