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authorBin Meng <bmeng.cn@gmail.com>2019-09-06 09:20:04 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-09-17 08:42:47 -0700
commite8c56787cd78f5d26285120f85bf898f5d3693b9 (patch)
treeb0fecb271860e7ad6c35fcf5763035e59913e931
parent91c985851dd57df3b003e7bd91f1cf544b3a288d (diff)
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riscv: hart: Add a "hartid-base" property to RISC-V hart array
At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
-rw-r--r--hw/riscv/riscv_hart.c3
-rw-r--r--include/hw/riscv/riscv_hart.h1
2 files changed, 3 insertions, 1 deletions
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 6620e41..5b98227 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -29,6 +29,7 @@
static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
+ DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
@@ -47,7 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
sizeof(RISCVCPU), cpu_type,
&error_abort, NULL);
- s->harts[idx].env.mhartid = idx;
+ s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
object_property_set_bool(OBJECT(&s->harts[idx]), true,
"realized", &err);
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 3b52b50..c75856f 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState {
/*< public >*/
uint32_t num_harts;
+ uint32_t hartid_base;
char *cpu_type;
RISCVCPU *harts;
} RISCVHartArrayState;