diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-20 17:35:36 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-20 17:35:36 +0100 |
commit | d3f5433c7b4aa2d59c6de4175743f4126e181aea (patch) | |
tree | 4f800d0b63205194e3049a23b378783e21b96d8a | |
parent | c51700273ad9802a21c19f8d2b4bcb67c38e74ac (diff) | |
parent | e3d038b89f1bf3f09da4d59aa16b16e8305e1a05 (diff) | |
download | qemu-d3f5433c7b4aa2d59c6de4175743f4126e181aea.zip qemu-d3f5433c7b4aa2d59c6de4175743f4126e181aea.tar.gz qemu-d3f5433c7b4aa2d59c6de4175743f4126e181aea.tar.bz2 |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
Machine/CPU/NUMA queue, 2017-09-19
# gpg: Signature made Tue 19 Sep 2017 21:17:01 BST
# gpg: using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request:
MAINTAINERS: Update git URLs for my trees
hw/acpi-build: Fix SRAT memory building in case of node 0 without RAM
NUMA: Replace MAX_NODES with nb_numa_nodes in for loop
numa: cpu: calculate/set default node-ids after all -numa CLI options are parsed
arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
pc: use generic cpu_model parsing
vl.c: convert cpu_model to cpu type and set of global properties before machine_init()
cpu: make cpu_generic_init() abort QEMU on error
qom: cpus: split cpu_generic_init() on feature parsing and cpu creation parts
hostmem-file: Add "discard-data" option
osdep: Define QEMU_MADV_REMOVE
vl: Clean up user-creatable objects when exiting
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
82 files changed, 307 insertions, 525 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 3d73597..e511ba7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -249,6 +249,7 @@ S: Maintained F: target/i386/ F: hw/i386/ F: disas/i386.c +T: git git://github.com/ehabkost/qemu.git x86-next Xtensa M: Max Filippov <jcmvbkbc@gmail.com> @@ -858,6 +859,7 @@ S: Supported F: hw/core/machine.c F: hw/core/null-machine.c F: include/hw/boards.h +T: git git://github.com/ehabkost/qemu.git machine-next Xtensa Machines --------------- @@ -1385,7 +1387,7 @@ M: Eduardo Habkost <ehabkost@redhat.com> S: Maintained F: numa.c F: include/sysemu/numa.h -T: git git://github.com/ehabkost/qemu.git numa +T: git git://github.com/ehabkost/qemu.git machine-next Host Memory Backends M: Eduardo Habkost <ehabkost@redhat.com> @@ -1393,6 +1395,7 @@ M: Igor Mammedov <imammedo@redhat.com> S: Maintained F: backends/hostmem*.c F: include/sysemu/hostmem.h +T: git git://github.com/ehabkost/qemu.git machine-next Cryptodev Backends M: Gonglei <arei.gonglei@huawei.com> diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c index fc4ef46..e44c319 100644 --- a/backends/hostmem-file.c +++ b/backends/hostmem-file.c @@ -32,6 +32,7 @@ struct HostMemoryBackendFile { HostMemoryBackend parent_obj; bool share; + bool discard_data; char *mem_path; }; @@ -103,16 +104,44 @@ static void file_memory_backend_set_share(Object *o, bool value, Error **errp) fb->share = value; } +static bool file_memory_backend_get_discard_data(Object *o, Error **errp) +{ + return MEMORY_BACKEND_FILE(o)->discard_data; +} + +static void file_memory_backend_set_discard_data(Object *o, bool value, + Error **errp) +{ + MEMORY_BACKEND_FILE(o)->discard_data = value; +} + +static void file_backend_unparent(Object *obj) +{ + HostMemoryBackend *backend = MEMORY_BACKEND(obj); + HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(obj); + + if (host_memory_backend_mr_inited(backend) && fb->discard_data) { + void *ptr = memory_region_get_ram_ptr(&backend->mr); + uint64_t sz = memory_region_size(&backend->mr); + + qemu_madvise(ptr, sz, QEMU_MADV_REMOVE); + } +} + static void file_backend_class_init(ObjectClass *oc, void *data) { HostMemoryBackendClass *bc = MEMORY_BACKEND_CLASS(oc); bc->alloc = file_backend_memory_alloc; + oc->unparent = file_backend_unparent; object_class_property_add_bool(oc, "share", file_memory_backend_get_share, file_memory_backend_set_share, &error_abort); + object_class_property_add_bool(oc, "discard-data", + file_memory_backend_get_discard_data, file_memory_backend_set_discard_data, + &error_abort); object_class_property_add_str(oc, "mem-path", get_mem_path, set_mem_path, &error_abort); diff --git a/bsd-user/main.c b/bsd-user/main.c index 8a6706a..836daac 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -902,10 +902,6 @@ int main(int argc, char **argv) /* NOTE: we need to init the CPU at this stage to get qemu_host_page_size */ cpu = cpu_init(cpu_model); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } env = cpu->env_ptr; #if defined(TARGET_SPARC) || defined(TARGET_PPC) cpu_reset(cpu); diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 1c5a177..1b12130 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -68,10 +68,6 @@ static void clipper_init(MachineState *machine) memset(cpus, 0, sizeof(cpus)); for (i = 0; i < smp_cpus; ++i) { cpus[i] = ALPHA_CPU(cpu_generic_init(TYPE_ALPHA_CPU, cpu_model)); - if (!cpus[i]) { - error_report("Unable to find CPU definition"); - exit(1); - } } cpus[0]->env.trap_arg0 = ram_size; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index b64a409..57a6806 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -151,10 +151,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd; Error *err = NULL; int i; - char **cpustr; - ObjectClass *oc; - const char *typename; - CPUClass *cc; if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -163,29 +159,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); - cpustr = g_strsplit(s->cpu_model, ",", 2); - - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); - if (!oc) { - error_setg(errp, "Unknown CPU model %s", cpustr[0]); - g_strfreev(cpustr); - return; - } - - cc = CPU_CLASS(oc); - typename = object_class_get_name(oc); - cc->parse_features(typename, cpustr[1], &err); - g_strfreev(cpustr); - if (err) { - error_propagate(errp, err); - return; - } - - s->cpu = ARM_CPU(object_new(typename)); - if (!s->cpu) { - error_setg(errp, "Unknown CPU model %s", s->cpu_model); - return; - } + s->cpu = ARM_CPU(object_new(s->cpu_type)); object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", &error_abort); @@ -241,7 +215,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) } static Property armv7m_properties[] = { - DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model), + DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), @@ -275,20 +249,16 @@ static void armv7m_reset(void *opaque) Returns the ARMv7M device. */ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, - const char *kernel_filename, const char *cpu_model) + const char *kernel_filename, const char *cpu_type) { DeviceState *armv7m; - if (cpu_model == NULL) { - cpu_model = "cortex-m3"; - } - armv7m = qdev_create(NULL, TYPE_ARMV7M); qdev_prop_set_uint32(armv7m, "num-irq", num_irq); - qdev_prop_set_string(armv7m, "cpu-model", cpu_model); + qdev_prop_set_string(armv7m, "cpu-type", cpu_type); object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()), "memory", &error_abort); - /* This will exit with an error if the user passed us a bad cpu_model */ + /* This will exit with an error if the user passed us a bad cpu_type */ qdev_init_nofail(armv7m); armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size); diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 13c6393..5aa3d2d 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = { static const AspeedSoCInfo aspeed_socs[] = { { .name = "ast2400-a0", - .cpu_model = "arm926", + .cpu_type = ARM_CPU_TYPE_NAME("arm926"), .silicon_rev = AST2400_A0_SILICON_REV, .sdram_base = AST2400_SDRAM_BASE, .sram_size = 0x8000, @@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .wdts_num = 2, }, { .name = "ast2400-a1", - .cpu_model = "arm926", + .cpu_type = ARM_CPU_TYPE_NAME("arm926"), .silicon_rev = AST2400_A1_SILICON_REV, .sdram_base = AST2400_SDRAM_BASE, .sram_size = 0x8000, @@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .wdts_num = 2, }, { .name = "ast2400", - .cpu_model = "arm926", + .cpu_type = ARM_CPU_TYPE_NAME("arm926"), .silicon_rev = AST2400_A0_SILICON_REV, .sdram_base = AST2400_SDRAM_BASE, .sram_size = 0x8000, @@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .wdts_num = 2, }, { .name = "ast2500-a1", - .cpu_model = "arm1176", + .cpu_type = ARM_CPU_TYPE_NAME("arm1176"), .silicon_rev = AST2500_A1_SILICON_REV, .sdram_base = AST2500_SDRAM_BASE, .sram_size = 0x9000, @@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj) { AspeedSoCState *s = ASPEED_SOC(obj); AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); - char *cpu_typename; int i; - cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model); - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename); + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); - g_free(cpu_typename); object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 8830192..f8c566e 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -18,7 +18,7 @@ #include "hw/block/flash.h" #include "sysemu/block-backend.h" #include "exec/address-spaces.h" -#include "qom/cpu.h" +#include "cpu.h" static struct arm_boot_info collie_binfo = { .loader_start = SA_SDCS0, @@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = { static void collie_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -35,11 +34,7 @@ static void collie_init(MachineState *machine) DriveInfo *dinfo; MemoryRegion *sysmem = get_system_memory(); - if (!cpu_model) { - cpu_model = "sa1110"; - } - - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model); + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type); dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000, @@ -65,6 +60,7 @@ static void collie_machine_init(MachineClass *mc) mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)"; mc->init = collie_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110"); } DEFINE_MACHINE("collie", collie_machine_init) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index ee1438a..e8e1d81 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) Exynos4210State *s = g_new(Exynos4210State, 1); qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; SysBusDevice *busdev; - ObjectClass *cpu_oc; DeviceState *dev; int i, n; - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); - assert(cpu_oc); - for (n = 0; n < EXYNOS4210_NCPUS; n++) { - Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); /* By default A9 CPUs have EL3 enabled. This board does not currently * support EL3 so the CPU EL3 property is disabled before realization. diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 092ce36..bba9e9f 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -44,6 +44,7 @@ #include "sysemu/block-backend.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" +#include "cpu.h" static const int sector_len = 128 * 1024; @@ -86,7 +87,6 @@ static void connex_init(MachineState *machine) static void verdex_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; PXA2xxState *cpu; DriveInfo *dinfo; int be; @@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine) uint32_t verdex_rom = 0x02000000; uint32_t verdex_ram = 0x10000000; - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: "pxa270-c0"); + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type); dinfo = drive_get(IF_PFLASH, 0, 0); if (!dinfo && !qtest_enabled()) { @@ -144,6 +144,7 @@ static void verdex_class_init(ObjectClass *oc, void *data) mc->desc = "Gumstix Verdex (PXA270)"; mc->init = verdex_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); } static const TypeInfo verdex_type = { diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index ba27789..354c6b2 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -222,7 +222,6 @@ enum cxmachines { static void calxeda_init(MachineState *machine, enum cxmachines machine_id) { ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -239,19 +238,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) switch (machine_id) { case CALXEDA_HIGHBANK: - cpu_model = "cortex-a9"; + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); break; case CALXEDA_MIDWAY: - cpu_model = "cortex-a15"; + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); break; + default: + assert(0); } for (n = 0; n < smp_cpus; n++) { - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); Object *cpuobj; ARMCPU *cpu; - cpuobj = object_new(object_class_get_name(oc)); + cpuobj = object_new(machine->cpu_type); cpu = ARM_CPU(cpuobj); object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index d603af9..e8303b8 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = { static void integratorcp_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - char **cpustr; - ObjectClass *cpu_oc; - CPUClass *cc; Object *cpuobj; ARMCPU *cpu; - const char *typename; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *ram_alias = g_new(MemoryRegion, 1); qemu_irq pic[32]; DeviceState *dev, *sic, *icp; int i; - Error *err = NULL; - if (!cpu_model) { - cpu_model = "arm926"; - } - - cpustr = g_strsplit(cpu_model, ",", 2); - - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); - if (!cpu_oc) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } - typename = object_class_get_name(cpu_oc); - - cc = CPU_CLASS(cpu_oc); - cc->parse_features(typename, cpustr[1], &err); - g_strfreev(cpustr); - if (err) { - error_report_err(err); - exit(1); - } - - cpuobj = object_new(typename); + cpuobj = object_new(machine->cpu_type); /* By default ARM1176 CPUs have EL3 enabled. This board does not * currently support EL3 so the CPU EL3 property is disabled before @@ -682,6 +655,7 @@ static void integratorcp_machine_init(MachineClass *mc) mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; mc->init = integratorcp_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); } DEFINE_MACHINE("integratorcp", integratorcp_machine_init) diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 637f52c..d07972a 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -24,6 +24,7 @@ #include "hw/sysbus.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" +#include "cpu.h" /* Device addresses */ #define MST_FPGA_PHYS 0x08000000 @@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, int i; int be; MemoryRegion *rom = g_new(MemoryRegion, 1); - const char *cpu_model = machine->cpu_model; - - if (!cpu_model) - cpu_model = "pxa270-c5"; /* Setup CPU & memory */ - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model); + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, + machine->cpu_type); memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM, &error_fatal); memory_region_set_readonly(rom, true); @@ -197,6 +195,7 @@ static void mainstone2_machine_init(MachineClass *mc) mc->desc = "Mainstone II (PXA27x)"; mc->init = mainstone_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); } DEFINE_MACHINE("mainstone", mainstone2_machine_init) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 769cff8..694fb36 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -46,7 +46,6 @@ typedef enum MPS2FPGAType { typedef struct { MachineClass parent; MPS2FPGAType fpga_type; - const char *cpu_model; uint32_t scc_id; } MPS2MachineClass; @@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine) MPS2MachineState *mms = MPS2_MACHINE(machine); MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); MemoryRegion *system_memory = get_system_memory(); + MachineClass *mc = MACHINE_GET_CLASS(machine); DeviceState *armv7m, *sccdev; - if (!machine->cpu_model) { - machine->cpu_model = mmc->cpu_model; - } - - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) { - error_report("This board can only be used with CPU %s", mmc->cpu_model); + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { + error_report("This board can only be used with CPU %s", + mc->default_cpu_type); exit(1); } @@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine) default: g_assert_not_reached(); } - qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model); + qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), "memory", &error_abort); object_property_set_bool(OBJECT(&mms->armv7m), true, "realized", @@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; mmc->fpga_type = FPGA_AN385; - mmc->cpu_model = "cortex-m3"; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); mmc->scc_id = 0x41040000 | (385 << 4); } @@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; mmc->fpga_type = FPGA_AN511; - mmc->cpu_model = "cortex-m3"; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); mmc->scc_id = 0x4104000 | (511 << 4); } diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index ab4ba31..b648770 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = { static void musicpal_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -1590,14 +1589,7 @@ static void musicpal_init(MachineState *machine) MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); - if (!cpu_model) { - cpu_model = "arm926"; - } - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } + cpu = ARM_CPU(cpu_create(machine->cpu_type)); /* For now we use a fixed - the original - RAM size */ memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", @@ -1719,6 +1711,7 @@ static void musicpal_machine_init(MachineClass *mc) mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; mc->init = musicpal_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); } DEFINE_MACHINE("musicpal", musicpal_machine_init) diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 9d34d4c..f936017 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine) DeviceState *dev; dev = qdev_create(NULL, TYPE_STM32F205_SOC); - qdev_prop_set_string(dev, "cpu-model", "cortex-m3"); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index a32ac82..58005b6 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine, struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); int sdram_size = binfo->ram_size; - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model); + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type); /* Setup peripherals * @@ -1426,6 +1426,7 @@ static void n800_class_init(ObjectClass *oc, void *data) mc->init = n800_init; mc->default_boot_order = ""; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); } static const TypeInfo n800_type = { @@ -1442,6 +1443,7 @@ static void n810_class_init(ObjectClass *oc, void *data) mc->init = n810_init; mc->default_boot_order = ""; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); } static const TypeInfo n810_type = { diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 400ba30..b3e7625 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, unsigned long sdram_size, - const char *core) + const char *cpu_type) { int i; struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); @@ -3858,16 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, DriveInfo *dinfo; SysBusDevice *busdev; - if (!core) - core = "ti925t"; - /* Core */ s->mpu_model = omap310; - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core)); - if (s->cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } + s->cpu = ARM_CPU(cpu_create(cpu_type)); s->sdram_size = sdram_size; s->sram_size = OMAP15XX_SRAM_SIZE; diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index ece25ae..3f6076e 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = { struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, unsigned long sdram_size, - const char *core) + const char *cpu_type) { struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); qemu_irq dma_irqs[4]; @@ -2261,11 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, /* Core */ s->mpu_model = omap2420; - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2")); - if (s->cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } + s->cpu = ARM_CPU(cpu_create(cpu_type)); s->sdram_size = sdram_size; s->sram_size = OMAP242X_SRAM_SIZE; diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 4535617..9a14270 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -36,6 +36,7 @@ #include "sysemu/block-backend.h" #include "sysemu/qtest.h" #include "exec/address-spaces.h" +#include "cpu.h" /*****************************************************************************/ /* Siemens SX1 Cellphone V1 */ @@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version) } mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, - machine->cpu_model); + machine->cpu_type); /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size, @@ -224,6 +225,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) mc->desc = "Siemens SX1 (OMAP310) V2"; mc->init = sx1_init_v2; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); } static const TypeInfo sx1_machine_v2_type = { @@ -239,6 +241,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) mc->desc = "Siemens SX1 (OMAP310) V1"; mc->init = sx1_init_v1; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); } static const TypeInfo sx1_machine_v1_type = { diff --git a/hw/arm/palm.c b/hw/arm/palm.c index bf070a2..b8753e2 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -29,6 +29,7 @@ #include "hw/devices.h" #include "hw/loader.h" #include "exec/address-spaces.h" +#include "cpu.h" static uint32_t static_readb(void *opaque, hwaddr offset) { @@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = { static void palmte_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine) MemoryRegion *flash = g_new(MemoryRegion, 1); MemoryRegion *cs = g_new(MemoryRegion, 4); - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model); + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type); /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "palmte.flash", flash_size, @@ -275,6 +275,7 @@ static void palmte_machine_init(MachineClass *mc) mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; mc->init = palmte_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); } DEFINE_MACHINE("cheetah", palmte_machine_init) diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index b0ac3cf..cf07234 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -2052,25 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level) /* Initialise a PXA270 integrated chip (ARM based core). */ PXA2xxState *pxa270_init(MemoryRegion *address_space, - unsigned int sdram_size, const char *revision) + unsigned int sdram_size, const char *cpu_type) { PXA2xxState *s; int i; DriveInfo *dinfo; s = g_new0(PXA2xxState, 1); - if (revision && strncmp(revision, "pxa27", 5)) { + if (strncmp(cpu_type, "pxa27", 5)) { fprintf(stderr, "Machine requires a PXA27x processor.\n"); exit(1); } - if (!revision) - revision = "pxa270"; - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision)); - if (s->cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } + s->cpu = ARM_CPU(cpu_create(cpu_type)); s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); /* SDRAM & Internal Memory Storage */ @@ -2196,11 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) s = g_new0(PXA2xxState, 1); - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255")); - if (s->cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); /* SDRAM & Internal Memory Storage */ diff --git a/hw/arm/realview.c b/hw/arm/realview.c index f3a49b6..87cd1e5 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -57,7 +57,6 @@ static void realview_init(MachineState *machine, { ARMCPU *cpu = NULL; CPUARMState *env; - ObjectClass *cpu_oc; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram_lo; MemoryRegion *ram_hi = g_new(MemoryRegion, 1); @@ -98,14 +97,8 @@ static void realview_init(MachineState *machine, break; } - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); - if (!cpu_oc) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } - for (n = 0; n < smp_cpus; n++) { - Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Object *cpuobj = object_new(machine->cpu_type); /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board * does not currently support EL3 so the CPU EL3 property is disabled @@ -361,33 +354,21 @@ static void realview_init(MachineState *machine, static void realview_eb_init(MachineState *machine) { - if (!machine->cpu_model) { - machine->cpu_model = "arm926"; - } realview_init(machine, BOARD_EB); } static void realview_eb_mpcore_init(MachineState *machine) { - if (!machine->cpu_model) { - machine->cpu_model = "arm11mpcore"; - } realview_init(machine, BOARD_EB_MPCORE); } static void realview_pb_a8_init(MachineState *machine) { - if (!machine->cpu_model) { - machine->cpu_model = "cortex-a8"; - } realview_init(machine, BOARD_PB_A8); } static void realview_pbx_a9_init(MachineState *machine) { - if (!machine->cpu_model) { - machine->cpu_model = "cortex-a9"; - } realview_init(machine, BOARD_PBX_A9); } @@ -399,6 +380,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data) mc->init = realview_eb_init; mc->block_default_type = IF_SCSI; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); } static const TypeInfo realview_eb_type = { @@ -416,6 +398,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_SCSI; mc->max_cpus = 4; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore"); } static const TypeInfo realview_eb_mpcore_type = { @@ -431,6 +414,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data) mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; mc->init = realview_pb_a8_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); } static const TypeInfo realview_pb_a8_type = { @@ -447,6 +431,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) mc->init = realview_pbx_a9_init; mc->max_cpus = 4; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); } static const TypeInfo realview_pbx_a9_type = { diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 6406421..feccdb0 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -30,6 +30,7 @@ #include "hw/sysbus.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "cpu.h" #undef REG_FMT #define REG_FMT "0x%02lx" @@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine, DeviceState *scp0, *scp1 = NULL; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *rom = g_new(MemoryRegion, 1); - const char *cpu_model = machine->cpu_model; - - if (!cpu_model) - cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; /* Setup CPU & memory */ - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model); + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, + machine->cpu_type); sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M); @@ -984,6 +982,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data) mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; mc->init = akita_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); } static const TypeInfo akitapda_type = { @@ -1000,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data) mc->init = spitz_init; mc->block_default_type = IF_IDE; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); } static const TypeInfo spitzpda_type = { @@ -1016,6 +1016,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data) mc->init = borzoi_init; mc->block_default_type = IF_IDE; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); } static const TypeInfo borzoipda_type = { @@ -1032,6 +1033,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data) mc->init = terrier_init; mc->block_default_type = IF_IDE; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); } static const TypeInfo terrierpda_type = { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index b3aad23..de7c0fc 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -22,6 +22,7 @@ #include "sysemu/sysemu.h" #include "hw/char/pl011.h" #include "hw/misc/unimp.h" +#include "cpu.h" #define GPIO_A 0 #define GPIO_B 1 @@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = { } }; -static void stellaris_init(const char *kernel_filename, const char *cpu_model, - stellaris_board_info *board) +static void stellaris_init(MachineState *ms, stellaris_board_info *board) { static const int uart_irq[] = {5, 6, 33, 34}; static const int timer_irq[] = {19, 21, 23, 35}; @@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, memory_region_add_subregion(system_memory, 0x20000000, sram); nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, - kernel_filename, cpu_model); + ms->kernel_filename, ms->cpu_type); qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, qemu_allocate_irq(&do_sys_reset, NULL, 0)); @@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, /* FIXME: Figure out how to generate these from stellaris_boards. */ static void lm3s811evb_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; - const char *kernel_filename = machine->kernel_filename; - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); + stellaris_init(machine, &stellaris_boards[0]); } static void lm3s6965evb_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; - const char *kernel_filename = machine->kernel_filename; - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); + stellaris_init(machine, &stellaris_boards[1]); } static void lm3s811evb_class_init(ObjectClass *oc, void *data) @@ -1454,6 +1450,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) mc->desc = "Stellaris LM3S811EVB"; mc->init = lm3s811evb_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); } static const TypeInfo lm3s811evb_type = { @@ -1469,6 +1466,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) mc->desc = "Stellaris LM3S6965EVB"; mc->init = lm3s6965evb_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); } static const TypeInfo lm3s6965evb_type = { diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index f61e735..1cd6374 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model); + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), "memory", &error_abort); object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) } static Property stm32f205_soc_properties[] = { - DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model), + DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 884242b..3d1a231 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1581,28 +1581,19 @@ static const TypeInfo strongarm_ssp_info = { /* Main CPU functions */ StrongARMState *sa1110_init(MemoryRegion *sysmem, - unsigned int sdram_size, const char *rev) + unsigned int sdram_size, const char *cpu_type) { StrongARMState *s; int i; s = g_new0(StrongARMState, 1); - if (!rev) { - rev = "sa1110-b5"; - } - - if (strncmp(rev, "sa1110", 6)) { + if (strncmp(cpu_type, "sa1110", 6)) { error_report("Machine requires a SA1110 processor."); exit(1); } - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev)); - - if (!s->cpu) { - error_report("Unable to find CPU definition"); - exit(1); - } + s->cpu = ARM_CPU(cpu_create(cpu_type)); memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram", sdram_size); diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 1134cf7..0447963 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = { static void tosa_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine) TC6393xbState *tmio; DeviceState *scp0, *scp1; - if (!cpu_model) - cpu_model = "pxa255"; - mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size); memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal); diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 76664e4..418792c 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -181,7 +181,6 @@ static struct arm_boot_info versatile_binfo; static void versatile_init(MachineState *machine, int board_id) { - ObjectClass *cpu_oc; Object *cpuobj; ARMCPU *cpu; MemoryRegion *sysmem = get_system_memory(); @@ -207,17 +206,7 @@ static void versatile_init(MachineState *machine, int board_id) exit(1); } - if (!machine->cpu_model) { - machine->cpu_model = "arm926"; - } - - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); - if (!cpu_oc) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } - - cpuobj = object_new(object_class_get_name(cpu_oc)); + cpuobj = object_new(machine->cpu_type); /* By default ARM1176 CPUs have EL3 enabled. This board does not * currently support EL3 so the CPU EL3 property is disabled before @@ -404,6 +393,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data) mc->init = vpb_init; mc->block_default_type = IF_SCSI; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); } static const TypeInfo versatilepb_type = { @@ -420,6 +410,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data) mc->init = vab_init; mc->block_default_type = IF_SCSI; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); } static const TypeInfo versatileab_type = { diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 96c5eeb..efb5a29 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -186,7 +186,7 @@ typedef struct { typedef void DBoardInitFn(const VexpressMachineState *machine, ram_addr_t ram_size, - const char *cpu_model, + const char *cpu_type, qemu_irq *pic); struct VEDBoardInfo { @@ -202,22 +202,16 @@ struct VEDBoardInfo { DBoardInitFn *init; }; -static void init_cpus(const char *cpu_model, const char *privdev, +static void init_cpus(const char *cpu_type, const char *privdev, hwaddr periphbase, qemu_irq *pic, bool secure) { - ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); DeviceState *dev; SysBusDevice *busdev; int n; - if (!cpu_oc) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } - /* Create the actual CPUs */ for (n = 0; n < smp_cpus; n++) { - Object *cpuobj = object_new(object_class_get_name(cpu_oc)); + Object *cpuobj = object_new(cpu_type); if (!secure) { object_property_set_bool(cpuobj, false, "has_el3", NULL); @@ -262,7 +256,7 @@ static void init_cpus(const char *cpu_model, const char *privdev, static void a9_daughterboard_init(const VexpressMachineState *vms, ram_addr_t ram_size, - const char *cpu_model, + const char *cpu_type, qemu_irq *pic) { MemoryRegion *sysmem = get_system_memory(); @@ -270,10 +264,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, MemoryRegion *lowram = g_new(MemoryRegion, 1); ram_addr_t low_ram_size; - if (!cpu_model) { - cpu_model = "cortex-a9"; - } - if (ram_size > 0x40000000) { /* 1GB is the maximum the address space permits */ fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); @@ -295,7 +285,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x60000000, ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ - init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); + init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ @@ -351,17 +341,13 @@ static VEDBoardInfo a9_daughterboard = { static void a15_daughterboard_init(const VexpressMachineState *vms, ram_addr_t ram_size, - const char *cpu_model, + const char *cpu_type, qemu_irq *pic) { MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); - if (!cpu_model) { - cpu_model = "cortex-a15"; - } - { /* We have to use a separate 64 bit variable here to avoid the gcc * "comparison is always false due to limited range of data type" @@ -380,7 +366,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x80000000, ram); /* 0x2c000000 A15MPCore private memory region (GIC) */ - init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); + init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); /* A15 daughterboard peripherals: */ @@ -560,7 +546,7 @@ static void vexpress_common_init(MachineState *machine) const hwaddr *map = daughterboard->motherboard_map; int i; - daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic); + daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); /* * If a bios file was provided, attempt to map it into memory @@ -761,6 +747,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data) VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); mc->desc = "ARM Versatile Express for Cortex-A9"; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); vmc->daughterboard = &a9_daughterboard; } @@ -771,6 +758,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data) VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); mc->desc = "ARM Versatile Express for Cortex-A15"; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); vmc->daughterboard = &a15_daughterboard; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index cfd834d..9e18b41 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -163,13 +163,13 @@ static const int a15irqmap[] = { }; static const char *valid_cpus[] = { - "cortex-a15", - "cortex-a53", - "cortex-a57", - "host", + ARM_CPU_TYPE_NAME("cortex-a15"), + ARM_CPU_TYPE_NAME("cortex-a53"), + ARM_CPU_TYPE_NAME("cortex-a57"), + ARM_CPU_TYPE_NAME("host"), }; -static bool cpuname_valid(const char *cpu) +static bool cpu_type_valid(const char *cpu) { int i; @@ -1259,18 +1259,8 @@ static void machvirt_init(MachineState *machine) MemoryRegion *secure_sysmem = NULL; int n, virt_max_cpus; MemoryRegion *ram = g_new(MemoryRegion, 1); - const char *cpu_model = machine->cpu_model; - char **cpustr; - ObjectClass *oc; - const char *typename; - CPUClass *cc; - Error *err = NULL; bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); - if (!cpu_model) { - cpu_model = "cortex-a15"; - } - /* We can probe only here because during property set * KVM is not available yet */ @@ -1287,11 +1277,8 @@ static void machvirt_init(MachineState *machine) } } - /* Separate the actual CPU model name from any appended features */ - cpustr = g_strsplit(cpu_model, ",", 2); - - if (!cpuname_valid(cpustr[0])) { - error_report("mach-virt: CPU %s not supported", cpustr[0]); + if (!cpu_type_valid(machine->cpu_type)) { + error_report("mach-virt: CPU type %s not supported", machine->cpu_type); exit(1); } @@ -1361,22 +1348,6 @@ static void machvirt_init(MachineState *machine) create_fdt(vms); - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); - if (!oc) { - error_report("Unable to find CPU definition"); - exit(1); - } - typename = object_class_get_name(oc); - - /* convert -smp CPU options specified by the user into global props */ - cc = CPU_CLASS(oc); - cc->parse_features(typename, cpustr[1], &err); - g_strfreev(cpustr); - if (err) { - error_report_err(err); - exit(1); - } - possible_cpus = mc->possible_cpu_arch_ids(machine); for (n = 0; n < possible_cpus->len; n++) { Object *cpuobj; @@ -1386,7 +1357,7 @@ static void machvirt_init(MachineState *machine) break; } - cpuobj = object_new(typename); + cpuobj = object_new(machine->cpu_type); object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, "mp-affinity", NULL); @@ -1583,6 +1554,11 @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) return possible_cpus->cpus[cpu_index].props; } +static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) +{ + return idx % nb_numa_nodes; +} + static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) { int n; @@ -1601,14 +1577,6 @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) virt_cpu_mp_affinity(vms, n); ms->possible_cpus->cpus[n].props.has_thread_id = true; ms->possible_cpus->cpus[n].props.thread_id = n; - - /* default distribution of CPUs over NUMA nodes */ - if (nb_numa_nodes) { - /* preset values but do not enable them i.e. 'has_node_id = false', - * numa init code will enable them later if manual mapping wasn't - * present on CLI */ - ms->possible_cpus->cpus[n].props.node_id = n % nb_numa_nodes; - } } return ms->possible_cpus; } @@ -1631,6 +1599,8 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->minimum_page_bits = 12; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = virt_cpu_index_to_props; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); + mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; } static const TypeInfo virt_machine_info = { diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3759cf8..1836a4e 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -158,11 +158,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, static void zynq_init(MachineState *machine) { ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - ObjectClass *cpu_oc; ARMCPU *cpu; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ext_ram = g_new(MemoryRegion, 1); @@ -174,12 +172,7 @@ static void zynq_init(MachineState *machine) qemu_irq pic[64]; int n; - if (!cpu_model) { - cpu_model = "cortex-a9"; - } - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); - - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); + cpu = ARM_CPU(object_new(machine->cpu_type)); /* By default A9 CPUs have EL3 enabled. This board does not * currently support EL3 so the CPU EL3 property is disabled before @@ -327,6 +320,7 @@ static void zynq_machine_init(MachineClass *mc) mc->max_cpus = 1; mc->no_sdcard = 1; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); } DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 417bc1a..60561c7 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -26,6 +26,7 @@ #include "audio/audio.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" +#include "cpu.h" #ifdef DEBUG_Z2 #define DPRINTF(fmt, ...) \ @@ -296,7 +297,6 @@ static const TypeInfo aer915_info = { static void z2_init(MachineState *machine) { - const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -309,12 +309,8 @@ static void z2_init(MachineState *machine) I2CBus *bus; DeviceState *wm; - if (!cpu_model) { - cpu_model = "pxa270-c5"; - } - /* Setup CPU & memory */ - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model); + mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type); #ifdef TARGET_WORDS_BIGENDIAN be = 1; @@ -371,6 +367,7 @@ static void z2_machine_init(MachineClass *mc) mc->desc = "Zipit Z2 (PXA27x)"; mc->init = z2_init; mc->ignore_memory_transaction_failures = true; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); } DEFINE_MACHINE("z2", z2_machine_init) diff --git a/hw/core/machine.c b/hw/core/machine.c index 41b53a1..80647ed 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -724,6 +724,7 @@ static void machine_numa_finish_init(MachineState *machine) /* fetch default mapping from board and enable it */ CpuInstanceProperties props = cpu_slot->props; + props.node_id = mc->get_default_cpu_node_id(machine, i); if (!default_mapping) { /* record slots with not set mapping, * TODO: make it hard error in future */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9776812..2af37a9 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2288,6 +2288,9 @@ build_tpm2(GArray *table_data, BIOSLinker *linker) (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); } +#define HOLE_640K_START (640 * 1024) +#define HOLE_640K_END (1024 * 1024) + static void build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) { @@ -2343,17 +2346,30 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) next_base = 0; numa_start = table_data->len; - numamem = acpi_data_push(table_data, sizeof *numamem); - build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED); - next_base = 1024 * 1024; for (i = 1; i < pcms->numa_nodes + 1; ++i) { mem_base = next_base; mem_len = pcms->node_mem[i - 1]; - if (i == 1) { - mem_len -= 1024 * 1024; - } next_base = mem_base + mem_len; + /* Cut out the 640K hole */ + if (mem_base <= HOLE_640K_START && + next_base > HOLE_640K_START) { + mem_len -= next_base - HOLE_640K_START; + if (mem_len > 0) { + numamem = acpi_data_push(table_data, sizeof *numamem); + build_srat_memory(numamem, mem_base, mem_len, i - 1, + MEM_AFFINITY_ENABLED); + } + + /* Check for the rare case: 640K < RAM < 1M */ + if (next_base <= HOLE_640K_END) { + next_base = HOLE_640K_END; + continue; + } + mem_base = HOLE_640K_END; + mem_len = next_base - HOLE_640K_END; + } + /* Cut out the ACPI_PCI hole */ if (mem_base <= pcms->below_4g_mem_size && next_base > pcms->below_4g_mem_size) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ef5f30e..05985d4 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1107,7 +1107,6 @@ static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) void pc_hot_add_cpu(const int64_t id, Error **errp) { - ObjectClass *oc; MachineState *ms = MACHINE(qdev_get_machine()); int64_t apic_id = x86_cpu_apic_id_from_index(id); Error *local_err = NULL; @@ -1124,9 +1123,7 @@ void pc_hot_add_cpu(const int64_t id, Error **errp) return; } - assert(ms->possible_cpus->cpus[0].cpu); /* BSP is always present */ - oc = OBJECT_CLASS(CPU_GET_CLASS(ms->possible_cpus->cpus[0].cpu)); - pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); + pc_new_cpu(ms->cpu_type, apic_id, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -1136,39 +1133,10 @@ void pc_hot_add_cpu(const int64_t id, Error **errp) void pc_cpus_init(PCMachineState *pcms) { int i; - CPUClass *cc; - ObjectClass *oc; - const char *typename; - gchar **model_pieces; const CPUArchIdList *possible_cpus; - MachineState *machine = MACHINE(pcms); + MachineState *ms = MACHINE(pcms); MachineClass *mc = MACHINE_GET_CLASS(pcms); - /* init CPUs */ - if (machine->cpu_model == NULL) { -#ifdef TARGET_X86_64 - machine->cpu_model = "qemu64"; -#else - machine->cpu_model = "qemu32"; -#endif - } - - model_pieces = g_strsplit(machine->cpu_model, ",", 2); - if (!model_pieces[0]) { - error_report("Invalid/empty CPU model name"); - exit(1); - } - - oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); - if (oc == NULL) { - error_report("Unable to find CPU definition: %s", model_pieces[0]); - exit(1); - } - typename = object_class_get_name(oc); - cc = CPU_CLASS(oc); - cc->parse_features(typename, model_pieces[1], &error_fatal); - g_strfreev(model_pieces); - /* Calculates the limit to CPU APIC ID values * * Limit for the APIC ID value, so that all @@ -1177,9 +1145,9 @@ void pc_cpus_init(PCMachineState *pcms) * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). */ pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; - possible_cpus = mc->possible_cpu_arch_ids(machine); + possible_cpus = mc->possible_cpu_arch_ids(ms); for (i = 0; i < smp_cpus; i++) { - pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal); + pc_new_cpu(ms->cpu_type, possible_cpus->cpus[i].arch_id, &error_fatal); } } @@ -2265,6 +2233,16 @@ pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) return possible_cpus->cpus[cpu_index].props; } +static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) +{ + X86CPUTopoInfo topo; + + assert(idx < ms->possible_cpus->len); + x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, + smp_cores, smp_threads, &topo); + return topo.pkg_id % nb_numa_nodes; +} + static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) { int i; @@ -2294,15 +2272,6 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].props.core_id = topo.core_id; ms->possible_cpus->cpus[i].props.has_thread_id = true; ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; - - /* default distribution of CPUs over NUMA nodes */ - if (nb_numa_nodes) { - /* preset values but do not enable them i.e. 'has_node_id = false', - * numa init code will enable them later if manual mapping wasn't - * present on CLI */ - ms->possible_cpus->cpus[i].props.node_id = - topo.pkg_id % nb_numa_nodes; - } } return ms->possible_cpus; } @@ -2347,6 +2316,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) pcmc->linuxboot_dma_enabled = true; mc->get_hotplug_handler = pc_get_hotpug_handler; mc->cpu_index_to_instance_props = pc_cpu_index_to_props; + mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; mc->has_hotpluggable_cpus = true; mc->default_boot_order = "cad"; @@ -2359,6 +2329,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) hc->unplug_request = pc_machine_device_unplug_request_cb; hc->unplug = pc_machine_device_unplug_cb; nc->nmi_monitor_handler = x86_nmi; + mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", pc_machine_get_hotplug_memory_region_size, NULL, diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b03cc04..9ff79b1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -378,9 +378,6 @@ static void pc_compat_0_13(MachineState *machine) static void pc_init_isa(MachineState *machine) { - if (!machine->cpu_model) { - machine->cpu_model = "486"; - } x86_cpu_change_kvm_default("kvm-pv-eoi", NULL); enable_compat_apic_id_mode(); pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, TYPE_I440FX_PCI_DEVICE); @@ -1113,6 +1110,7 @@ static void isapc_machine_options(MachineClass *m) pcmc->gigabyte_align = false; pcmc->smbios_legacy_mode = true; pcmc->has_reserved_memory = false; + m->default_cpu_type = X86_CPU_TYPE_NAME("486"); } DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa, diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c index eccf0ac..b0bb3ef 100644 --- a/hw/lm32/lm32_boards.c +++ b/hw/lm32/lm32_boards.c @@ -105,10 +105,6 @@ static void lm32_evr_init(MachineState *machine) cpu_model = "lm32-full"; } cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model); - exit(1); - } env = &cpu->env; reset_info->cpu = cpu; @@ -206,10 +202,6 @@ static void lm32_uclinux_init(MachineState *machine) cpu_model = "lm32-full"; } cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model); - exit(1); - } env = &cpu->env; reset_info->cpu = cpu; diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c index dffd879..4db4d2d 100644 --- a/hw/lm32/milkymist.c +++ b/hw/lm32/milkymist.c @@ -112,10 +112,6 @@ milkymist_init(MachineState *machine) cpu_model = "lm32-full"; } cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model); - exit(1); - } env = &cpu->env; reset_info->cpu = cpu; diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c index 7b9b15d..9002c46 100644 --- a/hw/m68k/an5206.c +++ b/hw/m68k/an5206.c @@ -43,10 +43,6 @@ static void an5206_init(MachineState *machine) cpu_model = "m5206"; } cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model)); - if (!cpu) { - error_report("Unable to find m68k CPU definition"); - exit(1); - } env = &cpu->env; /* Initialize CPU registers. */ diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 1a0f180..b9dde75 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -233,10 +233,6 @@ static void mcf5208evb_init(MachineState *machine) cpu_model = "m5208"; } cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model)); - if (!cpu) { - fprintf(stderr, "Unable to find m68k CPU definition\n"); - exit(1); - } env = &cpu->env; /* Initialize CPU registers. */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4ef337d..79d4c5e 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -72,10 +72,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) for (i = 0; i < s->num_vp; i++) { cpu = cpu_mips_init(s->cpu_model); - if (cpu == NULL) { - error_setg(errp, "%s: CPU initialization failed", __func__); - return; - } /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 3532399..439a3d7 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -281,10 +281,6 @@ static void mips_fulong2e_init(MachineState *machine) cpu_model = "Loongson-2E"; } cpu = cpu_mips_init(cpu_model); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index df2262a..ae10670 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -152,10 +152,6 @@ static void mips_jazz_init(MachineState *machine, cpu_model = "R4000"; } cpu = cpu_mips_init(cpu_model); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 7d6e583..e87cd32 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -932,10 +932,6 @@ static void create_cpu_without_cps(const char *cpu_model, for (i = 0; i < smp_cpus; i++) { cpu = cpu_mips_init(cpu_model); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index 07fc4c2..49cd38d 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -164,10 +164,6 @@ mips_mipssim_init(MachineState *machine) #endif } cpu = cpu_mips_init(cpu_model); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } env = &cpu->env; reset_info = g_malloc0(sizeof(ResetData)); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index b48a4d7..7efee94 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -194,10 +194,6 @@ void mips_r4k_init(MachineState *machine) #endif } cpu = cpu_mips_init(cpu_model); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } env = &cpu->env; reset_info = g_malloc0(sizeof(ResetData)); diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index 4c27b45..5ea8dd3 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -119,10 +119,6 @@ static void moxiesim_init(MachineState *machine) cpu_model = "MoxieLite-moxie-cpu"; } cpu = MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model)); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 243d802..86bf284 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -110,10 +110,6 @@ static void openrisc_sim_init(MachineState *machine) for (n = 0; n < smp_cpus; n++) { cpu = OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition!\n"); - exit(1); - } qemu_register_reset(main_cpu_reset, cpu); main_cpu_reset(cpu); } diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 55cad78..db0e49a 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -817,10 +817,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to initialize CPU!\n"); - exit(1); - } env = &cpu->env; cs = CPU(cpu); diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index d466634..33b46cb 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -189,10 +189,6 @@ static void ppc_core99_init(MachineState *machine) for (i = 0; i < smp_cpus; i++) { cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find PowerPC CPU definition\n"); - exit(1); - } env = &cpu->env; /* Set time-base frequency to 100 Mhz */ diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index fcac399..193b904 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -118,10 +118,6 @@ static void ppc_heathrow_init(MachineState *machine) for (i = 0; i < smp_cpus; i++) { cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find PowerPC CPU definition\n"); - exit(1); - } env = &cpu->env; /* Set time-base frequency to 16.6 Mhz */ diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index ca26398..f92d47f 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -187,10 +187,6 @@ static void bamboo_init(MachineState *machine) machine->cpu_model = "440EP"; } cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to initialize CPU!\n"); - exit(1); - } env = &cpu->env; if (env->mmu_model != POWERPC_MMU_BOOKE) { diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index ec90f13..6d7f785 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -57,11 +57,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_model, /* init CPUs */ cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find PowerPC %s CPU definition\n", - cpu_model); - exit(1); - } env = &cpu->env; cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 00f3321..94138a4 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -522,10 +522,6 @@ static void ppc_prep_init(MachineState *machine) for (i = 0; i < smp_cpus; i++) { cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find PowerPC CPU definition\n"); - exit(1); - } env = &cpu->env; if (env->flags & POWERPC_FLAG_RTC_CLK) { @@ -726,11 +722,6 @@ static void ibm_40p_init(MachineState *machine) machine->cpu_model = "604"; } cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); - if (!cpu) { - error_report("could not initialize CPU '%s'", - machine->cpu_model); - exit(1); - } env = &cpu->env; if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { error_report("only 6xx bus is supported on this machine"); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f680f28..17ea776 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3404,6 +3404,11 @@ spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) return core_slot->props; } +static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) +{ + return idx / smp_cores % nb_numa_nodes; +} + static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) { int i; @@ -3428,15 +3433,6 @@ static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) machine->possible_cpus->cpus[i].arch_id = core_id; machine->possible_cpus->cpus[i].props.has_core_id = true; machine->possible_cpus->cpus[i].props.core_id = core_id; - - /* default distribution of CPUs over NUMA nodes */ - if (nb_numa_nodes) { - /* preset values but do not enable them i.e. 'has_node_id = false', - * numa init code will enable them later if manual mapping wasn't - * present on CLI */ - machine->possible_cpus->cpus[i].props.node_id = - core_id / smp_threads / smp_cores % nb_numa_nodes; - } } return machine->possible_cpus; } @@ -3587,6 +3583,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) hc->pre_plug = spapr_machine_device_pre_plug; hc->plug = spapr_machine_device_plug; mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; + mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; hc->unplug_request = spapr_machine_device_unplug_request; diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index d5fdc16..ed9b406 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -97,10 +97,6 @@ static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size, qemu_irq *irqs; cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to initialize CPU!\n"); - exit(1); - } env = &cpu->env; ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 22bc534..16b9ed2 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -247,10 +247,6 @@ static void r2d_init(MachineState *machine) } cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } env = &cpu->env; reset_info = g_malloc0(sizeof(ResetData)); diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index 7f8a4b6..50ee36a 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -57,10 +57,6 @@ static void shix_init(MachineState *machine) cpu_model = "any"; cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(1); - } /* Allocate memory space */ memory_region_init_ram(rom, NULL, "shix.rom", 0x4000, &error_fatal); diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 56512ec..ec2816b 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -127,10 +127,6 @@ static void leon3_generic_hw_init(MachineState *machine) } cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); - exit(1); - } env = &cpu->env; cpu_sparc_set_id(env, 0); diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index cf47dca..e1bdd48 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -798,10 +798,6 @@ static void cpu_devinit(const char *cpu_model, unsigned int id, CPUSPARCState *env; cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); - exit(1); - } env = &cpu->env; cpu_sparc_set_id(env, id); diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index ecf38a4..097d529 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -354,10 +354,6 @@ SPARCCPU *sparc64_cpu_devinit(const char *cpu_model, cpu_model = default_cpu_model; } cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model)); - if (cpu == NULL) { - fprintf(stderr, "Unable to find Sparc CPU definition\n"); - exit(1); - } env = &cpu->env; env->tick = cpu_timer_create("tick", cpu, tick_irq, diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c index 3fcd8bb..0486f8a 100644 --- a/hw/tricore/tricore_testboard.c +++ b/hw/tricore/tricore_testboard.c @@ -75,10 +75,6 @@ static void tricore_testboard_init(MachineState *machine, int board_id) machine->cpu_model = "tc1796"; } cpu = TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, machine->cpu_model)); - if (!cpu) { - error_report("Unable to find CPU definition"); - exit(1); - } env = &cpu->env; memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram", 2 * 1024 * 1024, &error_fatal); diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index eb9862f..504ea46 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -128,10 +128,6 @@ static void puv3_init(MachineState *machine) } cpu = UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)); - if (!cpu) { - error_report("Unable to find CPU definition"); - exit(1); - } env = &cpu->env; puv3_soc_init(env); diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 1b4767f..b3580b1 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -85,11 +85,6 @@ static void xtensa_sim_init(MachineState *machine) for (n = 0; n < smp_cpus; n++) { cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)); - if (cpu == NULL) { - error_report("unable to find CPU definition '%s'", - cpu_model); - exit(EXIT_FAILURE); - } env = &cpu->env; env->sregs[PRID] = n; diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 182ec1e..a19cceb 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -233,11 +233,6 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine) for (n = 0; n < smp_cpus; n++) { cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)); - if (cpu == NULL) { - error_report("unable to find CPU definition '%s'", - cpu_model); - exit(EXIT_FAILURE); - } env = &cpu->env; env->sregs[PRID] = n; diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 10eb058..9ad316c 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -35,7 +35,7 @@ typedef struct { /* ARMv7M container object. * + Unnamed GPIO input lines: external IRQ lines for the NVIC * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ - * + Property "cpu-model": CPU model to instantiate + * + Property "cpu-type": CPU type to instantiate * + Property "num-irq": number of external IRQ lines * + Property "memory": MemoryRegion defining the physical address space * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal @@ -55,7 +55,7 @@ typedef struct ARMv7MState { MemoryRegion container; /* Properties */ - char *cpu_model; + char *cpu_type; /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ MemoryRegion *board_memory; } ARMv7MState; diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 0b88baa..f26914a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -49,7 +49,7 @@ typedef struct AspeedSoCState { typedef struct AspeedSoCInfo { const char *name; - const char *cpu_model; + const char *cpu_type; uint32_t silicon_rev; hwaddr sdram_base; uint64_t sram_size; diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index e2dce11..922a733 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -52,7 +52,7 @@ typedef struct STM32F205State { SysBusDevice parent_obj; /*< public >*/ - char *cpu_model; + char *cpu_type; ARMv7MState armv7m; diff --git a/include/hw/boards.h b/include/hw/boards.h index 7f044d1..156e0a5 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -123,8 +123,15 @@ typedef struct { * Returns an array of @CPUArchId architecture-dependent CPU IDs * which includes CPU IDs for present and possible to hotplug CPUs. * Caller is responsible for freeing returned list. + * @get_default_cpu_node_id: + * returns default board specific node_id value for CPU slot specified by + * index @idx in @ms->possible_cpus[] * @has_hotpluggable_cpus: * If true, board supports CPUs creation with -device/device_add. + * @default_cpu_type: + * specifies default CPU_TYPE, which will be used for parsing target + * specific features and for creating CPUs if CPU name wasn't provided + * explicitly at CLI * @minimum_page_bits: * If non-zero, the board promises never to create a CPU with a page size * smaller than this, so QEMU can use a more efficient larger page @@ -177,6 +184,7 @@ struct MachineClass { GArray *compat_props; const char *hw_version; ram_addr_t default_ram_size; + const char *default_cpu_type; bool option_rom_has_mr; bool rom_file_has_mr; int minimum_page_bits; @@ -191,6 +199,7 @@ struct MachineClass { CpuInstanceProperties (*cpu_index_to_instance_props)(MachineState *machine, unsigned cpu_index); const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine); + int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx); }; /** @@ -231,6 +240,7 @@ struct MachineState { char *kernel_cmdline; char *initrd_filename; const char *cpu_model; + const char *cpu_type; AccelState *accelerator; CPUArchIdList *possible_cpus; }; diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 9966638..72b75bf 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -273,6 +273,11 @@ void qemu_anon_ram_free(void *ptr, size_t size); #else #define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID #endif +#ifdef MADV_REMOVE +#define QEMU_MADV_REMOVE MADV_REMOVE +#else +#define QEMU_MADV_REMOVE QEMU_MADV_INVALID +#endif #elif defined(CONFIG_POSIX_MADVISE) @@ -285,6 +290,7 @@ void qemu_anon_ram_free(void *ptr, size_t size); #define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID #define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID #define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID +#define QEMU_MADV_REMOVE QEMU_MADV_INVALID #else /* no-op */ @@ -297,6 +303,7 @@ void qemu_anon_ram_free(void *ptr, size_t size); #define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID #define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID #define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID +#define QEMU_MADV_REMOVE QEMU_MADV_INVALID #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 0dc767a..0efebdb 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -645,6 +645,28 @@ void cpu_reset(CPUState *cpu); ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); /** + * cpu_create: + * @typename: The CPU type. + * + * Instantiates a CPU and realizes the CPU. + * + * Returns: A #CPUState or %NULL if an error occurred. + */ +CPUState *cpu_create(const char *typename); + +/** + * cpu_parse_cpu_model: + * @typename: The CPU base type or CPU type. + * @cpu_model: The model string including optional parameters. + * + * processes optional parameters and registers them as global properties + * + * Returns: type of CPU to create or prints error and terminates process + * if an error occurred. + */ +const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model); + +/** * cpu_generic_init: * @typename: The CPU base type. * @cpu_model: The model string including optional parameters. diff --git a/include/qom/object_interfaces.h b/include/qom/object_interfaces.h index d63c1c2..d23e11b 100644 --- a/include/qom/object_interfaces.h +++ b/include/qom/object_interfaces.h @@ -147,4 +147,12 @@ int user_creatable_add_opts_foreach(void *opaque, */ void user_creatable_del(const char *id, Error **errp); +/** + * user_creatable_cleanup: + * + * Delete all user-creatable objects and the user-creatable + * objects container. + */ +void user_creatable_cleanup(void); + #endif diff --git a/linux-user/main.c b/linux-user/main.c index 03666ef..829f974 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4323,10 +4323,6 @@ int main(int argc, char **argv, char **envp) /* NOTE: we need to init the CPU at this stage to get qemu_host_page_size */ cpu = cpu_init(cpu_model); - if (!cpu) { - fprintf(stderr, "Unable to find CPU definition\n"); - exit(EXIT_FAILURE); - } env = cpu->env_ptr; cpu_reset(cpu); @@ -567,7 +567,7 @@ void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, } memory_region_init(mr, owner, name, ram_size); - for (i = 0; i < MAX_NODES; i++) { + for (i = 0; i < nb_numa_nodes; i++) { uint64_t size = numa_info[i].node_mem; HostMemoryBackend *backend = numa_info[i].node_memdev; if (!backend) { diff --git a/qemu-options.hx b/qemu-options.hx index 600614f..77859a2 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4182,7 +4182,7 @@ property must be set. These objects are placed in the @table @option -@item -object memory-backend-file,id=@var{id},size=@var{size},mem-path=@var{dir},share=@var{on|off} +@item -object memory-backend-file,id=@var{id},size=@var{size},mem-path=@var{dir},share=@var{on|off},discard-data=@var{on|off} Creates a memory file backend object, which can be used to back the guest RAM with huge pages. The @option{id} parameter is a @@ -4194,6 +4194,12 @@ the path to either a shared memory or huge page filesystem mount. The @option{share} boolean option determines whether the memory region is marked as private to QEMU, or shared. The latter allows a co-operating external process to access the QEMU memory region. +Setting the @option{discard-data} boolean option to @var{on} +indicates that file contents can be destroyed when QEMU exits, +to avoid unnecessarily flushing data to the backing file. Note +that @option{discard-data} is only an optimization, and QEMU +might not discard file contents if it aborts unexpectedly or is +terminated using SIGKILL. @item -object rng-random,id=@var{id},filename=@var{/dev/random} @@ -54,43 +54,48 @@ bool cpu_exists(int64_t id) return !!cpu_by_arch_id(id); } -CPUState *cpu_generic_init(const char *typename, const char *cpu_model) +CPUState *cpu_create(const char *typename) +{ + Error *err = NULL; + CPUState *cpu = CPU(object_new(typename)); + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + exit(EXIT_FAILURE); + } + return cpu; +} + +const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model) { - CPUState *cpu = NULL; ObjectClass *oc; CPUClass *cc; - Error *err = NULL; gchar **model_pieces; + const char *cpu_type; model_pieces = g_strsplit(cpu_model, ",", 2); oc = cpu_class_by_name(typename, model_pieces[0]); if (oc == NULL) { + error_report("unable to find CPU model '%s'", model_pieces[0]); g_strfreev(model_pieces); - return NULL; + exit(EXIT_FAILURE); } + cpu_type = object_class_get_name(oc); cc = CPU_CLASS(oc); - /* TODO: all callers of cpu_generic_init() need to be converted to - * call parse_features() only once, before calling cpu_generic_init(). - */ - cc->parse_features(object_class_get_name(oc), model_pieces[1], &err); + cc->parse_features(cpu_type, model_pieces[1], &error_fatal); g_strfreev(model_pieces); - if (err != NULL) { - goto out; - } - - cpu = CPU(object_new(object_class_get_name(oc))); - object_property_set_bool(OBJECT(cpu), true, "realized", &err); - -out: - if (err != NULL) { - error_report_err(err); - object_unref(OBJECT(cpu)); - return NULL; - } + return cpu_type; +} - return cpu; +CPUState *cpu_generic_init(const char *typename, const char *cpu_model) +{ + /* TODO: all callers of cpu_generic_init() need to be converted to + * call cpu_parse_features() only once, before calling cpu_generic_init(). + */ + return cpu_create(cpu_parse_cpu_model(typename, cpu_model)); } bool cpu_paging_enabled(const CPUState *cpu) diff --git a/qom/object_interfaces.c b/qom/object_interfaces.c index 3bb8959..6824a88 100644 --- a/qom/object_interfaces.c +++ b/qom/object_interfaces.c @@ -193,6 +193,11 @@ void user_creatable_del(const char *id, Error **errp) object_unparent(obj); } +void user_creatable_cleanup(void) +{ + object_unparent(object_get_objects_root()); +} + static void register_types(void) { static const TypeInfo uc_interface_info = { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 412e94c..20a3445 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -911,7 +911,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) } cpuname = g_strsplit(cpu_model, ",", 1); - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); + typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5a1f957..6e50ae2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2091,6 +2091,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) +#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) + #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4b0fa06..0aa28fc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -705,9 +705,6 @@ void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) /* CPU class name definitions: */ -#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU -#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) - /* Return type name for a given CPU model name * Caller is responsible for freeing the returned string. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0f80de1..b086b15 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1510,6 +1510,15 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model) +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) + +#ifdef TARGET_X86_64 +#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") +#else +#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") +#endif + #define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list @@ -4716,6 +4716,16 @@ int main(int argc, char **argv, char **envp) current_machine->boot_order = boot_order; current_machine->cpu_model = cpu_model; + + /* parse features once if machine provides default cpu_type */ + if (machine_class->default_cpu_type) { + current_machine->cpu_type = machine_class->default_cpu_type; + if (cpu_model) { + current_machine->cpu_type = + cpu_parse_cpu_model(machine_class->default_cpu_type, cpu_model); + } + } + machine_run_board_init(current_machine); realtime_init(); @@ -4887,6 +4897,7 @@ int main(int argc, char **argv, char **envp) audio_cleanup(); monitor_cleanup(); qemu_chr_cleanup(); + user_creatable_cleanup(); /* TODO: unref root container, check all devices are ok */ return 0; |