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authorDaniel P. Berrangé <berrange@redhat.com>2022-12-16 07:57:46 -0500
committerMichael S. Tsirkin <mst@redhat.com>2022-12-21 06:35:28 -0500
commitc8c7c406db49a8bdf6b9e0962c4ec66a25ca1e5d (patch)
treea5639329294bff950520edf7f429f4a2cf511709
parent23d8e32499a03a68e7ceef79600aed4d965480e0 (diff)
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hw/isa: add trace events for ICH9 LPC chip config access
These tracepoints aid in understanding and debugging the guest drivers for the TCO watchdog. Reviewed-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20221216125749.596075-3-berrange@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-rw-r--r--hw/isa/lpc_ich9.c3
-rw-r--r--hw/isa/trace-events4
2 files changed, 7 insertions, 0 deletions
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 6c44cc9..cea7392 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -52,6 +52,7 @@
#include "hw/nvram/fw_cfg.h"
#include "qemu/cutils.h"
#include "hw/acpi/acpi_aml_interface.h"
+#include "trace.h"
/*****************************************************************************/
/* ICH9 LPC PCI to ISA bridge */
@@ -162,6 +163,7 @@ static void ich9_cc_write(void *opaque, hwaddr addr,
{
ICH9LPCState *lpc = (ICH9LPCState *)opaque;
+ trace_ich9_cc_write(addr, val, len);
ich9_cc_addr_len(&addr, &len);
memcpy(lpc->chip_config + addr, &val, len);
pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
@@ -177,6 +179,7 @@ static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
uint32_t val = 0;
ich9_cc_addr_len(&addr, &len);
memcpy(&val, lpc->chip_config + addr, len);
+ trace_ich9_cc_read(addr, val, len);
return val;
}
diff --git a/hw/isa/trace-events b/hw/isa/trace-events
index b8f877e..c4567a9 100644
--- a/hw/isa/trace-events
+++ b/hw/isa/trace-events
@@ -21,3 +21,7 @@ via_pm_io_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len 0x%
via_pm_io_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len 0x%x"
via_superio_read(uint8_t addr, uint8_t val) "addr 0x%x val 0x%x"
via_superio_write(uint8_t addr, uint32_t val) "addr 0x%x val 0x%x"
+
+# lpc_ich9.c
+ich9_cc_write(uint64_t addr, uint64_t val, unsigned len) "addr=0x%"PRIx64 " val=0x%"PRIx64 " len=%u"
+ich9_cc_read(uint64_t addr, uint64_t val, unsigned len) "addr=0x%"PRIx64 " val=0x%"PRIx64 " len=%u"