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| author | Song Gao <gaosong@loongson.cn> | 2023-02-27 15:10:46 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-03-03 09:37:30 +0800 |
| commit | c77432d0efc56273347eb5d8619935052e5ad0a6 (patch) | |
| tree | c1624b2fdda17195d67dc3f905b0b32a5c1be557 | |
| parent | 5f4c96b779f9b556c3a0e925382a387c222df002 (diff) | |
| download | qemu-c77432d0efc56273347eb5d8619935052e5ad0a6.zip qemu-c77432d0efc56273347eb5d8619935052e5ad0a6.tar.gz qemu-c77432d0efc56273347eb5d8619935052e5ad0a6.tar.bz2 | |
target/loongarch: Implement Chip Configuraiton Version Register(0x0000)
According to the 3A5000 manual 4.1 implement Chip Configuration
Version Register(0x0000).
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230227071046.1445572-1-gaosong@loongson.cn>
| -rw-r--r-- | target/loongarch/cpu.c | 2 | ||||
| -rw-r--r-- | target/loongarch/cpu.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d6513f2..97e6579 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -546,6 +546,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr, static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) { switch (addr) { + case VERSION_REG: + return 0x11ULL; case FEATURE_REG: return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 1ULL << IOCSRF_CSRIPI; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index d60693f..e11c875 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -28,6 +28,7 @@ #define IOCSRF_GMOD 9 #define IOCSRF_VM 11 +#define VERSION_REG 0x0 #define FEATURE_REG 0x8 #define VENDOR_REG 0x10 #define CPUNAME_REG 0x20 |