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authoryang.zhang <yang.zhang@hexintek.com>2023-07-07 11:23:06 +0800
committerAlistair Francis <alistair.francis@wdc.com>2023-07-10 22:29:15 +1000
commitc5cc248b478bc21e50845ba6b2414c4a688e195f (patch)
tree446e7ba209b478a4f4a2cc7516d6312802748451
parent32b2d75bf7fab6fa82dd01b2413ca14753b90973 (diff)
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target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly
Should set/get riscv all reg timer,i.e, time/compare/frequency/state. Signed-off-by: Yang Zhang <yang.zhang@hexintek.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230707032306.4606-1-gaoshanliukou@163.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--target/riscv/kvm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0f932a5..c3976a5 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -99,7 +99,7 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
do { \
- int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), &reg); \
+ int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), &reg); \
if (ret) { \
abort(); \
} \