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| author | Richard Henderson <rth@twiddle.net> | 2012-08-20 16:41:05 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:18:37 -0800 |
| commit | b9836c1acd4ecb286bd1617857cc52df7b75c414 (patch) | |
| tree | 7e64b1655c3edbfdb54df4c88baba2d49b0ba669 | |
| parent | d9a39927993a186b039d5be66cc85c0e735a78bc (diff) | |
| download | qemu-b9836c1acd4ecb286bd1617857cc52df7b75c414.zip qemu-b9836c1acd4ecb286bd1617857cc52df7b75c414.tar.gz qemu-b9836c1acd4ecb286bd1617857cc52df7b75c414.tar.bz2 | |
target-s390: Convert SUPERVISOR CALL
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-s390x/insn-data.def | 3 | ||||
| -rw-r--r-- | target-s390x/translate.c | 34 |
2 files changed, 22 insertions, 15 deletions
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 69af25d..7a0c999 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -337,6 +337,9 @@ C(0xe399, SLB, RXY_a, Z, r1, m2_32u, new, r1_32, subb, subb32) C(0xe389, SLBG, RXY_a, Z, r1, m2_64, r1, 0, subb, subb64) +/* SUPERVISOR CALL */ + C(0x0a00, SVC, I, Z, 0, 0, 0, 0, svc, 0) + /* TEST UNDER MASK */ C(0x9100, TM, SI, Z, m1_8u, i2_8u, 0, 0, 0, tm32) C(0xeb51, TMY, SIY, LD, m1_8u, i2_8u, 0, 0, 0, tm32) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 26ca49b..e2b7671 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2371,21 +2371,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) LOG_DISAS("opc 0x%x\n", opc); switch (opc) { - case 0xa: /* SVC I [RR] */ - insn = ld_code2(env, s->pc); - debug_insn(insn); - i = insn & 0xff; - update_psw_addr(s); - gen_op_calc_cc(s); - tmp32_1 = tcg_const_i32(i); - tmp32_2 = tcg_const_i32(s->next_pc - s->pc); - tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, int_svc_code)); - tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); - gen_exception(EXCP_SVC); - s->is_jmp = DISAS_EXCP; - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - break; case 0xe: /* MVCL R1,R2 [RR] */ insn = ld_code2(env, s->pc); decode_rr(s, insn, &r1, &r2); @@ -3717,6 +3702,25 @@ static ExitStatus op_subb(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_svc(DisasContext *s, DisasOps *o) +{ + TCGv_i32 t; + + update_psw_addr(s); + gen_op_calc_cc(s); + + t = tcg_const_i32(get_field(s->fields, i1) & 0xff); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); + tcg_temp_free_i32(t); + + t = tcg_const_i32(s->next_pc - s->pc); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); + tcg_temp_free_i32(t); + + gen_exception(EXCP_SVC); + return EXIT_NORETURN; +} + static ExitStatus op_xor(DisasContext *s, DisasOps *o) { tcg_gen_xor_i64(o->out, o->in1, o->in2); |