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authorRichard Henderson <richard.henderson@linaro.org>2022-04-29 14:16:01 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-06-28 04:35:07 +0530
commita1df4bab432fc62a0d14abc192ce063c432afd2e (patch)
tree1ede5861bf64d56e61dd7f1e6eb1f23c3777118c
parent3c820ddc1b92f17fea85fdaed2928feaa9c238d7 (diff)
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semihosting: Split out common_semi_has_synccache
We already have some larger ifdef blocks for ARM and RISCV; split out a boolean test for SYS_SYNCCACHE. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--semihosting/arm-compat-semi.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 7550dce..50f40a2 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -224,6 +224,12 @@ static inline target_ulong common_semi_stack_bottom(CPUState *cs)
CPUARMState *env = &cpu->env;
return is_a64(env) ? env->xregs[31] : env->regs[13];
}
+
+static inline bool common_semi_has_synccache(CPUArchState *env)
+{
+ /* Ok for A64, invalid for A32/T32. */
+ return is_a64(env);
+}
#endif /* TARGET_ARM */
#ifdef TARGET_RISCV
@@ -260,6 +266,11 @@ static inline target_ulong common_semi_stack_bottom(CPUState *cs)
CPURISCVState *env = &cpu->env;
return env->gpr[xSP];
}
+
+static inline bool common_semi_has_synccache(CPUArchState *env)
+{
+ return true;
+}
#endif
/*
@@ -1102,16 +1113,11 @@ void do_common_semihosting(CPUState *cs)
* virtual address range. This is a nop for us since we don't
* implement caches. This is only present on A64.
*/
-#ifdef TARGET_ARM
- if (is_a64(cs->env_ptr)) {
+ if (common_semi_has_synccache(env)) {
common_semi_set_ret(cs, 0);
break;
}
-#endif
-#ifdef TARGET_RISCV
- common_semi_set_ret(cs, 0);
-#endif
- /* fall through -- invalid for A32/T32 */
+ /* fall through */
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
cpu_dump_state(cs, stderr, 0);