diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-28 04:40:26 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-07-28 04:40:26 -0700 |
| commit | a17001c42329f809c7f1768925b8089324564312 (patch) | |
| tree | 11acbd2f94ea248a918be60a3bba79c8f64ec3d9 | |
| parent | 3e4abe2c92964aadd35344a635b0f32cb487fd5c (diff) | |
| parent | 54f218363052be210e77d2ada8c0c1e51b3ad6cd (diff) | |
| download | qemu-a17001c42329f809c7f1768925b8089324564312.zip qemu-a17001c42329f809c7f1768925b8089324564312.tar.gz qemu-a17001c42329f809c7f1768925b8089324564312.tar.bz2 | |
Merge tag 'pull-riscv-to-apply-20220728' of github.com:alistair23/qemu into staging
Sixth RISC-V PR for QEMU 7.1
This is a PR to go in for RC1. It fixes a segfault that occurs
when using multiple sockets on the RISC-V virt board. It also
includes a small fix to allow both Zmmul and M extensions.
* Allow both Zmmul and M extension
* Fix multi-socket plic configuraiton
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmLh33AACgkQIeENKd+X
# cFROBQf/QFxHsIX9clpAkHmK220efQ3rjHZtdCqQoCeRZp2EytFS9KZ6iae/BM9r
# 3Z8cZci38kxjqTzsYJLj46yNO3AxHoFsDH41yWTMOsxjVWVlno/06R/C1B4Ek37N
# kZXWKHzqfQvZRJIUAjKfVxaLtw9xRI9xYqWxVngdYSoW3HWHHz5UmA6fFoJ29QiZ
# SKEgxhakrqhvN9GMm1aWGkLN10uD5lFWOBMYdqMVcWq48XSP3Df5FU2Xk0sfegXq
# EqbIYKJL/Q6koyvmdpQz7VmtMAGjMTcmozEH8oN/MuCk7MCLmbloWVl+LF39SeTH
# 3amapiJBtYBOwaNZUpb5TZkv/bEDIw==
# =ip1R
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 27 Jul 2022 05:59:28 PM PDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220728' of github.com:alistair23/qemu:
hw/intc: sifive_plic: Fix multi-socket plic configuraiton
RISC-V: Allow both Zmmul and M
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | hw/intc/sifive_plic.c | 4 | ||||
| -rw-r--r-- | target/riscv/cpu.c | 5 |
2 files changed, 2 insertions, 7 deletions
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 56d60e9..af4ae36 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -454,10 +454,10 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, for (i = 0; i < plic->num_addrs; i++) { int cpu_num = plic->addr_config[i].hartid; - CPUState *cpu = qemu_get_cpu(hartid_base + cpu_num); + CPUState *cpu = qemu_get_cpu(cpu_num); if (plic->addr_config[i].mode == PLICMode_M) { - qdev_connect_gpio_out(dev, num_harts + cpu_num, + qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num, qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); } if (plic->addr_config[i].mode == PLICMode_S) { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973..ac6f82e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -619,11 +619,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_ifencei = true; } - if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) { - warn_report("Zmmul will override M"); - cpu->cfg.ext_m = false; - } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); |