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| author | Alistair Francis <Alistair.Francis@wdc.com> | 2018-12-19 19:20:09 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-12-26 06:40:02 +1100 |
| commit | 91468b2703ee0e4dcd7439dec8ca60d6cf8270ac (patch) | |
| tree | 5a37521db589662d7e6e1c5bc1b83b1eb66c004e | |
| parent | 464e447a0c4fbda2c5adce9a1b0f96800648a36f (diff) | |
| download | qemu-91468b2703ee0e4dcd7439dec8ca60d6cf8270ac.zip qemu-91468b2703ee0e4dcd7439dec8ca60d6cf8270ac.tar.gz qemu-91468b2703ee0e4dcd7439dec8ca60d6cf8270ac.tar.bz2 | |
disas: Add RISC-V support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <caa478c8987d6042434bb9582017cdf0ea192208.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | disas.c | 10 |
1 files changed, 8 insertions, 2 deletions
@@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size) # ifdef _ARCH_PPC64 s.info.cap_mode = CS_MODE_64; # endif -#elif defined(__riscv__) - print_insn = print_insn_riscv; +#elif defined(__riscv) && defined(CONFIG_RISCV_DIS) +#if defined(_ILP32) || (__riscv_xlen == 32) + print_insn = print_insn_riscv32; +#elif defined(_LP64) + print_insn = print_insn_riscv64; +#else +#error unsupported RISC-V ABI +#endif #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS) print_insn = print_insn_arm_a64; s.info.cap_arch = CS_ARCH_ARM64; |