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| author | Richard Henderson <rth@twiddle.net> | 2012-09-05 09:38:22 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:18:39 -0800 |
| commit | 7df3e93aa953148841bd8a086cb3230f3d01a14c (patch) | |
| tree | e310ca5dc10674711efdedc42b741ef4793a53df | |
| parent | 145cdb401995707d1261735da7f6be3d4a91d377 (diff) | |
| download | qemu-7df3e93aa953148841bd8a086cb3230f3d01a14c.zip qemu-7df3e93aa953148841bd8a086cb3230f3d01a14c.tar.gz qemu-7df3e93aa953148841bd8a086cb3230f3d01a14c.tar.bz2 | |
target-s390: Convert LAM, STAM
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-s390x/insn-data.def | 6 | ||||
| -rw-r--r-- | target-s390x/translate.c | 46 |
2 files changed, 28 insertions, 24 deletions
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 9859b3b..2e09838 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -279,6 +279,9 @@ C(0xeb04, LMG, RSY_a, Z, 0, a2, 0, 0, lm64, 0) /* LOAD MULTIPLE HIGH */ C(0xeb96, LMH, RSY_a, Z, 0, a2, 0, 0, lmh, 0) +/* LOAD ACCESS MULTIPLE */ + C(0x9a00, LAM, RS_a, Z, 0, a2, 0, 0, lam, 0) + C(0xeb9a, LAMY, RSY_a, LD, 0, a2, 0, 0, lam, 0) /* MOVE */ C(0xe544, MVHHI, SIL, GIE, la1, i2, 0, m1_16, mov2, 0) @@ -389,6 +392,9 @@ D(0xeb24, STMG, RSY_a, Z, 0, a2, 0, 0, stm, 0, 8) /* STORE MULTIPLE HIGH */ C(0xeb26, STMH, RSY_a, Z, 0, a2, 0, 0, stmh, 0) +/* STORE ACCESS MULTIPLE */ + C(0x9b00, STAM, RS_a, Z, 0, a2, 0, 0, stam, 0) + C(0xeb9b, STAMY, RSY_a, LD, 0, a2, 0, 0, stam, 0) /* SUBTRACT */ C(0x1b00, SR, RR_a, Z, r1, r2, new, r1_32, sub, subs32) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 8425c51..b2a258f 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2233,30 +2233,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) LOG_DISAS("opc 0x%x\n", opc); switch (opc) { - case 0x9a: /* LAM R1,R3,D2(B2) [RS] */ - insn = ld_code4(env, s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); - tmp32_1 = tcg_const_i32(r1); - tmp32_2 = tcg_const_i32(r3); - potential_page_fault(s); - gen_helper_lam(cpu_env, tmp32_1, tmp, tmp32_2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - break; - case 0x9b: /* STAM R1,R3,D2(B2) [RS] */ - insn = ld_code4(env, s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); - tmp32_1 = tcg_const_i32(r1); - tmp32_2 = tcg_const_i32(r3); - potential_page_fault(s); - gen_helper_stam(cpu_env, tmp32_1, tmp, tmp32_2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - break; case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */ insn = ld_code4(env, s->pc); decode_rs(s, insn, &r1, &r3, &b2, &d2); @@ -3265,6 +3241,17 @@ static ExitStatus op_lpsw(DisasContext *s, DisasOps *o) } #endif +static ExitStatus op_lam(DisasContext *s, DisasOps *o) +{ + TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); + TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); + potential_page_fault(s); + gen_helper_lam(cpu_env, r1, o->in2, r3); + tcg_temp_free_i32(r1); + tcg_temp_free_i32(r3); + return NO_EXIT; +} + static ExitStatus op_lm32(DisasContext *s, DisasOps *o) { int r1 = get_field(s->fields, r1); @@ -3518,6 +3505,17 @@ static ExitStatus op_st64(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_stam(DisasContext *s, DisasOps *o) +{ + TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); + TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); + potential_page_fault(s); + gen_helper_stam(cpu_env, r1, o->in2, r3); + tcg_temp_free_i32(r1); + tcg_temp_free_i32(r3); + return NO_EXIT; +} + static ExitStatus op_stm(DisasContext *s, DisasOps *o) { int r1 = get_field(s->fields, r1); |