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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-04-23 12:09:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-04 10:32:46 +0100 |
| commit | 5a89dd2385a193aa954a7c9bf4e381f2ba6ae359 (patch) | |
| tree | 0086852a3758dfbfeb8a88fbe49455a00521f77c | |
| parent | ce3125bed935a12e619a8253c19340ecaa899347 (diff) | |
| download | qemu-5a89dd2385a193aa954a7c9bf4e381f2ba6ae359.zip qemu-5a89dd2385a193aa954a7c9bf4e381f2ba6ae359.tar.gz qemu-5a89dd2385a193aa954a7c9bf4e381f2ba6ae359.tar.bz2 | |
target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers. The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register. For
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
this 64-bit ID register would end up always zero. Luckily at the
moment that's what they should be anyway, so this bug has no visible
effects.
Use the right-sized variable.
Fixes: 3bec78447a958d481991
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200423110915.10527-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/cpu64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e232c0e..9bdf75b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -710,9 +710,9 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ cpu->isar.id_mmfr4 = u; - u = cpu->isar.id_aa64dfr0; - u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ - cpu->isar.id_aa64dfr0 = u; + t = cpu->isar.id_aa64dfr0; + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 = t; u = cpu->isar.id_dfr0; u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ |