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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-06-13 16:18:51 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-06-29 10:04:57 -0700 |
| commit | 50a7470e3e9de7fda510acd02880f85ad6d5afd5 (patch) | |
| tree | 6186c5d6c84efbf30659d1d96880261d18a579e2 | |
| parent | 2b0a39e51e64ae501192b18233bddcc81c098312 (diff) | |
| download | qemu-50a7470e3e9de7fda510acd02880f85ad6d5afd5.zip qemu-50a7470e3e9de7fda510acd02880f85ad6d5afd5.tar.gz qemu-50a7470e3e9de7fda510acd02880f85ad6d5afd5.tar.bz2 | |
target/arm: Improve vector REV
We can eliminate the requirement for a zero-extended output,
because the following store will ignore any garbage high bits.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/arm/translate-a64.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 304fd3d..1a40e49 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12444,12 +12444,10 @@ static void handle_rev(DisasContext *s, int opcode, bool u, read_vec_element(s, tcg_tmp, rn, i, grp_size); switch (grp_size) { case MO_16: - tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp, - TCG_BSWAP_IZ | TCG_BSWAP_OZ); + tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ); break; case MO_32: - tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, - TCG_BSWAP_IZ | TCG_BSWAP_OZ); + tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ); break; case MO_64: tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); |