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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-04-10 15:14:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-04-10 15:14:36 +0100 |
| commit | 26aeb3b5894e0f3d17354e306002c59fa060e1c5 (patch) | |
| tree | e84b30b9e698972932fa5daff610350e61678f02 | |
| parent | 08dede07030973c1053868bc64de7e10bfa02ad6 (diff) | |
| parent | 8539dc00552e8ea60420856fc1262c8299bc6308 (diff) | |
| download | qemu-26aeb3b5894e0f3d17354e306002c59fa060e1c5.zip qemu-26aeb3b5894e0f3d17354e306002c59fa060e1c5.tar.gz qemu-26aeb3b5894e0f3d17354e306002c59fa060e1c5.tar.bz2 | |
Merge tag 'pull-target-arm-20230410' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm: Fix bug where we weren't initializing
guarded bit state when combining S1/S2 attrs
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# gpg: Signature made Mon 10 Apr 2023 15:12:11 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230410' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Copy guarded bit in combine_cacheattrs
target/arm: PTE bit GP only applies to stage1
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/ptw.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ec3f517..6d72950 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1585,11 +1585,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.secure = false; } - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.guarded = extract64(attrs, 50, 1); /* GP */ - } - if (regime_is_stage2(mmu_idx)) { result->cacheattrs.is_s2_format = true; result->cacheattrs.attrs = extract32(attrs, 2, 4); @@ -1600,6 +1595,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, assert(attrindx <= 7); result->cacheattrs.is_s2_format = false; result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.guarded = extract64(attrs, 50, 1); /* GP */ + } } /* @@ -2576,6 +2576,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, assert(!s1.is_s2_format); ret.is_s2_format = false; + ret.guarded = s1.guarded; if (s1.attrs == 0xf0) { tagged = true; |