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| author | Francisco Iglesias <frasse.iglesias@gmail.com> | 2022-04-12 00:18:36 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-05-16 16:15:40 -0400 |
| commit | 1f1a7b226923c655530d6bbe7d85d87e3df2d6f1 (patch) | |
| tree | c35a8f2cea78fd3e457094912e696b654bd7d0c0 | |
| parent | 8e58f6ec24f64b7d88f2b01d39049011f5097fae (diff) | |
| download | qemu-1f1a7b226923c655530d6bbe7d85d87e3df2d6f1.zip qemu-1f1a7b226923c655530d6bbe7d85d87e3df2d6f1.tar.gz qemu-1f1a7b226923c655530d6bbe7d85d87e3df2d6f1.tar.bz2 | |
include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX
According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
bus number, this makes the ECAM max size equal to '1 << 28'. This patch
restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
changed in commit 58d5b22bbd5 ("ppc4xx: Add device models found in PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | include/hw/pci/pcie_host.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index b3c8ce9..82d9217 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -65,7 +65,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, * bit 12 - 14: function number * bit 0 - 11: offset in configuration space of a given device */ -#define PCIE_MMCFG_SIZE_MAX (1ULL << 29) +#define PCIE_MMCFG_SIZE_MAX (1ULL << 28) #define PCIE_MMCFG_SIZE_MIN (1ULL << 20) #define PCIE_MMCFG_BUS_BIT 20 #define PCIE_MMCFG_BUS_MASK 0xff |