diff options
author | Marc MarĂ <marc.mari.barcelo@gmail.com> | 2015-02-24 17:34:14 +0100 |
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committer | Kevin Wolf <kwolf@redhat.com> | 2015-03-10 14:02:23 +0100 |
commit | 1e34cf9681ec549e26f30daaabc1ce58d60446f7 (patch) | |
tree | 264d8f96a4c4ea26c54a9b17ba29dae51db28df5 | |
parent | 833a7cc36e63653641558ba27148076f9a32062f (diff) | |
download | qemu-1e34cf9681ec549e26f30daaabc1ce58d60446f7.zip qemu-1e34cf9681ec549e26f30daaabc1ce58d60446f7.tar.gz qemu-1e34cf9681ec549e26f30daaabc1ce58d60446f7.tar.bz2 |
libqos: Solve bug in interrupt checking when using MSIX in virtio-pci.c
The MSIX interrupt was always acked without checking its value, which caused a
race condition. If the ISR was raised between the read and the acking, the ISR
was never detected and it timed out.
Signed-off-by: Marc MarĂ <marc.mari.barcelo@gmail.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Tested-by: John Snow <jsnow@redhat.com>
Message-id: 1424795655-16952-1-git-send-email-marc.mari.barcelo@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
-rw-r--r-- | tests/libqos/virtio-pci.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index 046a316..f9fb924 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -142,8 +142,12 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq) return qpci_msix_pending(dev->pdev, vqpci->msix_entry); } else { data = readl(vqpci->msix_addr); - writel(vqpci->msix_addr, 0); - return data == vqpci->msix_data; + if (data == vqpci->msix_data) { + writel(vqpci->msix_addr, 0); + return true; + } else { + return false; + } } } else { return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 1; @@ -162,8 +166,12 @@ static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d) return qpci_msix_pending(dev->pdev, dev->config_msix_entry); } else { data = readl(dev->config_msix_addr); - writel(dev->config_msix_addr, 0); - return data == dev->config_msix_data; + if (data == dev->config_msix_data) { + writel(dev->config_msix_addr, 0); + return true; + } else { + return false; + } } } else { return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 2; |