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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-11-20 11:15:34 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-12-16 12:45:20 +0000 |
| commit | 1d725ae952a14b30c84b7bc81b218b8ba77dd311 (patch) | |
| tree | 2b41de5acdbf012a5b877817e6a0bf0c5573fd27 | |
| parent | cbb26c9a122c3f71fb53989817d406a2f6d08662 (diff) | |
| download | qemu-1d725ae952a14b30c84b7bc81b218b8ba77dd311.zip qemu-1d725ae952a14b30c84b7bc81b218b8ba77dd311.tar.gz qemu-1d725ae952a14b30c84b7bc81b218b8ba77dd311.tar.bz2 | |
target-mips: Also apply the CP0.Status mask to MTTC0
Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places. Also preserve the
current values of masked out bits.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| -rw-r--r-- | target-mips/op_helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1267ef2..7e632f6 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1413,9 +1413,10 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - other->CP0_Status = arg1 & ~0xf1000018; + other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); sync_c0_status(env, other, other_tc); } |