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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:13 +0100 |
| commit | 0e7b176ae01d5a664d4cbf619a7315819494e6cb (patch) | |
| tree | d838ef227e2471cb0bfa9635958d7847040ff221 | |
| parent | 14e5f106073d67e5a00a8f29a017550b0436bde8 (diff) | |
| download | qemu-0e7b176ae01d5a664d4cbf619a7315819494e6cb.zip qemu-0e7b176ae01d5a664d4cbf619a7315819494e6cb.tar.gz qemu-0e7b176ae01d5a664d4cbf619a7315819494e6cb.tar.bz2 | |
target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"
For the CPU type "any" (only used with linux-user) we were reporting
the L1Ip field as 0b00, which is reserved. Change this field to 0b10
instead, indicating a VIPT icache as the comment describes.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 1412966807-20844-1-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | target-arm/cpu64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index a95367a..bb778b3 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -151,7 +151,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); - cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */ + cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ } #endif |