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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-16 22:53:33 +0200 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2021-06-05 20:58:43 +0200 |
| commit | 0d42cd5c1d370701c9f17367115244fbaedd2ea1 (patch) | |
| tree | d5e84625c043bc11d5726f350445159d78bc3d3e | |
| parent | 6f398e533f5e259b4f937f4aa9de970f7201d166 (diff) | |
| download | qemu-0d42cd5c1d370701c9f17367115244fbaedd2ea1.zip qemu-0d42cd5c1d370701c9f17367115244fbaedd2ea1.tar.gz qemu-0d42cd5c1d370701c9f17367115244fbaedd2ea1.tar.bz2 | |
target/riscv: Do not include 'pmp.h' in user emulation
Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210516205333.696094-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7e879fb..0619b49 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,7 +97,9 @@ enum { typedef struct CPURISCVState CPURISCVState; +#if !defined(CONFIG_USER_ONLY) #include "pmp.h" +#endif #define RV_VLEN_MAX 256 |