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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-04-04 11:14:58 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-06-28 14:27:59 +0200 |
| commit | 0573997713eb0a37ab98b545794e18b868b471ea (patch) | |
| tree | 660734e8d6763952abf9a9b1d268fd37b0e5e198 | |
| parent | cf43b5b69c0f4acee52e3648b88f4a0bf3de770b (diff) | |
| download | qemu-0573997713eb0a37ab98b545794e18b868b471ea.zip qemu-0573997713eb0a37ab98b545794e18b868b471ea.tar.gz qemu-0573997713eb0a37ab98b545794e18b868b471ea.tar.bz2 | |
target/ppc: Restrict KVM-specific fields from ArchCPU
The 'kvm_sw_tlb' and 'tlb_dirty' fields introduced in commit
93dd5e852c ("kvm: ppc: booke206: use MMU API") are specific
to KVM and shouldn't be accessed when it is not available.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230624192645.13680-1-philmd@linaro.org>
| -rw-r--r-- | hw/ppc/e500.c | 2 | ||||
| -rw-r--r-- | hw/ppc/ppce500_spin.c | 2 | ||||
| -rw-r--r-- | target/ppc/cpu.h | 2 | ||||
| -rw-r--r-- | target/ppc/mmu_common.c | 4 |
4 files changed, 10 insertions, 0 deletions
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b6eb599..67793a8 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -765,7 +765,9 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env) tlb->mas7_3 = 0; tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; +#ifdef CONFIG_KVM env->tlb_dirty = true; +#endif } static void ppce500_cpu_reset_sec(void *opaque) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index d57b199..bbce63e 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -83,7 +83,9 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M; tlb->mas7_3 = pa & TARGET_PAGE_MASK; tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; +#ifdef CONFIG_KVM env->tlb_dirty = true; +#endif } static void spin_kick(CPUState *cs, run_on_cpu_data data) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 94497aa..af12c93 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1149,8 +1149,10 @@ struct CPUArchState { int nb_pids; /* Number of available PID registers */ int tlb_type; /* Type of TLB we're dealing with */ ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ +#ifdef CONFIG_KVM bool tlb_dirty; /* Set to non-zero when modifying TLB */ bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ +#endif /* CONFIG_KVM */ uint32_t tlb_need_flush; /* Delayed flush needed */ #define TLB_NEED_LOCAL_FLUSH 0x1 #define TLB_NEED_GLOBAL_FLUSH 0x2 diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index ae1db6e..8c000e2 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -930,10 +930,12 @@ static void mmubooke_dump_mmu(CPUPPCState *env) ppcemb_tlb_t *entry; int i; +#ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { qemu_printf("Cannot access KVM TLB\n"); return; } +#endif qemu_printf("\nTLB:\n"); qemu_printf("Effective Physical Size PID Prot " @@ -1021,10 +1023,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env) int offset = 0; int i; +#ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { qemu_printf("Cannot access KVM TLB\n"); return; } +#endif for (i = 0; i < BOOKE206_MAX_TLBN; i++) { int size = booke206_tlb_size(env, i); |