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| author | Richard Braun <rbraun@sceen.net> | 2018-02-22 15:12:51 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-22 15:12:51 +0000 |
| commit | f6bfe45af2a9bd1b929955ca3bf54726d1e68d88 (patch) | |
| tree | 192a87b7baeb70244561b22df6442fbda77eebf4 /.travis.yml | |
| parent | 1c3db49d39d66646ff546ec26f36e3b9040f3504 (diff) | |
| download | qemu-f6bfe45af2a9bd1b929955ca3bf54726d1e68d88.zip qemu-f6bfe45af2a9bd1b929955ca3bf54726d1e68d88.tar.gz qemu-f6bfe45af2a9bd1b929955ca3bf54726d1e68d88.tar.bz2 | |
hw/char/stm32f2xx_usart: fix TXE/TC bit handling
I/O currently being synchronous, there is no reason to ever clear the
SR_TXE bit. However the SR_TC bit may be cleared by software writing
to the SR register, so set it on each write.
In addition, fix the reset value of the USART status register.
Signed-off-by: Richard Braun <rbraun@sceen.net>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
[PMM: removed XXX tag from comment, since it isn't something
we need to come back and fix in QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions