Merge patch series "target/riscv: Some updates to float point related extensions"

RISC-V defines a handful of extensions related to floating point, along
with various relationships between these and other extensions.  This
patch set adds support for the Zvfh, Zvhfmin, and Zve64d extensions;
along with a handful of fixes and cleanups related to the other
floating-point extension relationships.

* b4-shazam-merge
  target/riscv: Expose properties for Zv* extensions
  target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
  target/riscv: Fix check for vector load/store instructions when EEW=64
  target/riscv: Add support for Zvfh/zvfhmin extensions
  target/riscv: Remove rebundunt check for zve32f and zve64f
  target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
  target/riscv: Simplify check for Zve32f and Zve64f
  target/riscv: Indent fixes in cpu.c
  target/riscv: Add propertie check for Zvfh{min} extensions
  target/riscv: Fix relationship between V, Zve*, F and D
  target/riscv: Add cfg properties for Zv* extensions
  target/riscv: Simplify the check for Zfhmin and Zhinxmin
  target/riscv: Fix the relationship between Zhinxmin and Zhinx
  target/riscv: Fix the relationship between Zfhmin and Zfh

Message-ID: <20230215020539.4788-1-liweiwei@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

0 files changed, 0 insertions, 0 deletions