From 474ee5a81880dcf60789e7c2a3054b3afb34c3ca Mon Sep 17 00:00:00 2001 From: Michael Clark Date: Mon, 21 May 2018 13:29:31 +1200 Subject: RISC-V: Support separate firmware and kernel payload Support for separate firmware and kernel payload is added by updating BBL to read optional preloaded kernel address attributes from device-tree using a similar mechanism to that used to pass init ramdisk addresses to linux kernel. chosen { riscv,kernel-start = <0x00000000 0x80200000>; riscv,kernel-end = <0x00000000 0x80590634>; }; These attributes are added by QEMU and read by BBL when combining -bios and -kernel options. e.g. $ qemu-system-riscv64 -machine virt -bios bbl -kernel vmlinux With this change, bbl can be compiled without --with-payload and the dummy payload alignment is altered to make the memory footprint of the firmware-only bbl smaller. The dummy payload message is updated to indicate the alternative load method. This load method could also be supported by a first stage boot loader that reads seperate firmware and kernel from SPI flash. The main advantage of this new mechanism is that it eases kernel development by avoiding the riscv-pk packaging step after kernel builds, makes building per repository artefacts for CI simpler, and mimics bootloaders on other platforms that can load a kernel image file directly. Ultimately BBL should use an SPI driver to load the kernel image however this mechanism supports use cases such such as QEMU's -bios, -kernel and -initrd options following examples from other platforms that pass kernel entry to firmware via device-tree. Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- bbl/payload.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'bbl/payload.S') diff --git a/bbl/payload.S b/bbl/payload.S index 6a175aa..b6797aa 100644 --- a/bbl/payload.S +++ b/bbl/payload.S @@ -1,7 +1,15 @@ +#include "config.h" #include "encoding.h" .section ".payload","a",@progbits + +#if RELAXED_ALIGNMENT + /* align payload minimally */ + .align 3 +#else + /* align payload to megapage */ .align RISCV_PGSHIFT + RISCV_PGLEVEL_BITS +#endif .globl _payload_start, _payload_end _payload_start: -- cgit v1.1