From d3a541bcee38f15fc2aee3edfc1bc6f5b6e9b1be Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Thu, 30 Aug 2012 17:41:11 -0700
Subject: set status register correctly for rv32

---
 pk/riscv-pk.S | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/pk/riscv-pk.S b/pk/riscv-pk.S
index f1fe216..635bc29 100644
--- a/pk/riscv-pk.S
+++ b/pk/riscv-pk.S
@@ -13,7 +13,11 @@ _start:
   add t0, t0, %lo(trap_entry)
   mtpcr t0, ASM_CR(PCR_EVEC)
 
+#ifdef __riscv64
   li t0, SR_S | SR_PS | SR_ET | SR_EC | SR_S64
+#else
+  li t0, SR_S | SR_PS | SR_ET | SR_EC
+#endif
   or t1, t0, SR_EF | SR_EV
   mtpcr t1, ASM_CR(PCR_SR)
   mfpcr t1, ASM_CR(PCR_SR)
-- 
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