From a43d87cf0ae16acff8763130f0c7e40014616cff Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 6 Mar 2014 18:49:41 -0800 Subject: Add fclass.{s|d} instructions --- pk/encoding.h | 6 ++++++ pk/fp.c | 4 ++++ softfloat/f32_classify.c | 33 +++++++++++++++++++++++++++++++++ softfloat/f64_classify.c | 33 +++++++++++++++++++++++++++++++++ softfloat/softfloat.h | 2 ++ softfloat/softfloat.mk.in | 2 ++ softfloat_riscv/softfloat_riscv.mk.in | 3 --- softfloat_riscv/softfloat_types.h | 3 +++ softfloat_riscv/specialize.h | 3 +-- 9 files changed, 84 insertions(+), 5 deletions(-) create mode 100755 softfloat/f32_classify.c create mode 100755 softfloat/f64_classify.c diff --git a/pk/encoding.h b/pk/encoding.h index 8a4a342..74f72bd 100644 --- a/pk/encoding.h +++ b/pk/encoding.h @@ -145,6 +145,8 @@ #define MASK_SLTIU 0x707f #define MATCH_FADD_S 0x53 #define MASK_FADD_S 0xfe00007f +#define MATCH_FCLASS_D 0xea000053 +#define MASK_FCLASS_D 0xfff0707f #define MATCH_FCVT_S_W 0x70000053 #define MASK_FCVT_S_W 0xfff0007f #define MATCH_MUL 0x2000033 @@ -197,6 +199,8 @@ #define MASK_BLT 0x707f #define MATCH_SCALL 0x73 #define MASK_SCALL 0xffffffff +#define MATCH_FCLASS_S 0xe8000053 +#define MASK_FCLASS_S 0xfff0707f #define MATCH_SC_W 0x1800202f #define MASK_SC_W 0xf800707f #define MATCH_REM 0x2006033 @@ -487,6 +491,7 @@ DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) @@ -513,6 +518,7 @@ DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) DECLARE_INSN(rem, MATCH_REM, MASK_REM) DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) diff --git a/pk/fp.c b/pk/fp.c index 5848448..537dc23 100644 --- a/pk/fp.c +++ b/pk/fp.c @@ -192,6 +192,10 @@ int emulate_fp(trapframe_t* tf) XRDR = f32_to_ui64(frs1s, softfloat_roundingMode, true); else if(IS_INSN(FCVT_LU_D)) XRDR = f64_to_ui64(frs1d, softfloat_roundingMode, true); + else if(IS_INSN(FCLASS_S)) + XRDR = f32_classify(frs1s); + else if(IS_INSN(FCLASS_D)) + XRDR = f64_classify(frs1s); else return -1; diff --git a/softfloat/f32_classify.c b/softfloat/f32_classify.c new file mode 100755 index 0000000..d16aa25 --- /dev/null +++ b/softfloat/f32_classify.c @@ -0,0 +1,33 @@ + +#include +#include +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f32_classify( float32_t a ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + + uA.f = a; + uiA = uA.ui; + + uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF; + uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0; + bool sign = signF32UI( uiA ); + + return + ( sign && infOrNaN && fracF32UI( uiA ) == 0 ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && fracF32UI( uiA ) ) << 2 | + ( sign && subnormalOrZero && fracF32UI( uiA ) == 0 ) << 3 | + ( !sign && infOrNaN && fracF32UI( uiA ) == 0 ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && fracF32UI( uiA ) ) << 5 | + ( !sign && subnormalOrZero && fracF32UI( uiA ) == 0 ) << 4 | + ( isNaNF32UI( uiA ) && softfloat_isSigNaNF32UI( uiA )) << 8 | + ( isNaNF32UI( uiA ) && !softfloat_isSigNaNF32UI( uiA )) << 9; +} + diff --git a/softfloat/f64_classify.c b/softfloat/f64_classify.c new file mode 100755 index 0000000..2ec124b --- /dev/null +++ b/softfloat/f64_classify.c @@ -0,0 +1,33 @@ + +#include +#include +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f64_classify( float64_t a ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + + uA.f = a; + uiA = uA.ui; + + uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF; + uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0; + bool sign = signF64UI( uiA ); + + return + ( sign && infOrNaN && fracF64UI( uiA ) == 0 ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && fracF64UI( uiA ) ) << 2 | + ( sign && subnormalOrZero && fracF64UI( uiA ) == 0 ) << 3 | + ( !sign && infOrNaN && fracF64UI( uiA ) == 0 ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && fracF64UI( uiA ) ) << 5 | + ( !sign && subnormalOrZero && fracF64UI( uiA ) == 0 ) << 4 | + ( isNaNF64UI( uiA ) && softfloat_isSigNaNF64UI( uiA )) << 8 | + ( isNaNF64UI( uiA ) && !softfloat_isSigNaNF64UI( uiA )) << 9; +} + diff --git a/softfloat/softfloat.h b/softfloat/softfloat.h index 3eddeed..e989a55 100755 --- a/softfloat/softfloat.h +++ b/softfloat/softfloat.h @@ -128,6 +128,7 @@ bool f32_eq_signaling( float32_t, float32_t ); bool f32_le_quiet( float32_t, float32_t ); bool f32_lt_quiet( float32_t, float32_t ); bool f32_isSignalingNaN( float32_t ); +uint_fast16_t f32_classify( float32_t a ); /*---------------------------------------------------------------------------- | 64-bit (double-precision) floating-point operations. @@ -158,6 +159,7 @@ bool f64_eq_signaling( float64_t, float64_t ); bool f64_le_quiet( float64_t, float64_t ); bool f64_lt_quiet( float64_t, float64_t ); bool f64_isSignalingNaN( float64_t ); +uint_fast16_t f64_classify( float64_t a ); /*---------------------------------------------------------------------------- | Extended double-precision rounding precision. Valid values are 32, 64, and diff --git a/softfloat/softfloat.mk.in b/softfloat/softfloat.mk.in index 59993cb..0914b3b 100644 --- a/softfloat/softfloat.mk.in +++ b/softfloat/softfloat.mk.in @@ -31,6 +31,7 @@ softfloat_c_srcs = \ f32_to_ui32_r_minMag.c \ f32_to_ui64.c \ f32_to_ui64_r_minMag.c \ + f32_classify.c \ f64_add.c \ f64_div.c \ f64_eq.c \ @@ -55,6 +56,7 @@ softfloat_c_srcs = \ f64_to_ui32_r_minMag.c \ f64_to_ui64.c \ f64_to_ui64_r_minMag.c \ + f64_classify.c \ i32_to_f32.c \ i32_to_f64.c \ i64_to_f32.c \ diff --git a/softfloat_riscv/softfloat_riscv.mk.in b/softfloat_riscv/softfloat_riscv.mk.in index 0b898ed..94ab3a3 100644 --- a/softfloat_riscv/softfloat_riscv.mk.in +++ b/softfloat_riscv/softfloat_riscv.mk.in @@ -7,12 +7,9 @@ softfloat_riscv_hdrs = \ softfloat_riscv_c_srcs = \ softfloat_raiseFlags.c \ - s_commonNaNToF32UI.c \ s_commonNaNToF64UI.c \ s_f32UIToCommonNaN.c \ s_f64UIToCommonNaN.c \ - s_isSigNaNF32UI.c \ - s_isSigNaNF64UI.c \ s_propagateNaNF32UI.c \ s_propagateNaNF64UI.c \ diff --git a/softfloat_riscv/softfloat_types.h b/softfloat_riscv/softfloat_types.h index 9fada89..215f5e3 100755 --- a/softfloat_riscv/softfloat_types.h +++ b/softfloat_riscv/softfloat_types.h @@ -12,5 +12,8 @@ typedef uint64_t float64_t; typedef struct { uint64_t v; uint16_t x; } floatx80_t; typedef struct { uint64_t v[ 2 ]; } float128_t; +#define INLINE inline +#define INLINE_LEVEL 1 + #endif diff --git a/softfloat_riscv/specialize.h b/softfloat_riscv/specialize.h index bf57bc9..91e2e0b 100755 --- a/softfloat_riscv/specialize.h +++ b/softfloat_riscv/specialize.h @@ -32,8 +32,7 @@ these four paragraphs for those parts of this code that are retained. =============================================================================*/ -#include -#include +#include "softfloat_types.h" /*---------------------------------------------------------------------------- *----------------------------------------------------------------------------*/ -- cgit v1.1