From 43c14ea417d21968d918447662a1c4722a3887d2 Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Tue, 5 Nov 2013 21:09:11 -0800
Subject: sync pcr.h, correctly name SR_EA

---
 pk/handlers.c | 26 ++++++--------------------
 pk/pcr.h      | 19 ++++++-------------
 pk/pk.S       |  8 ++++----
 3 files changed, 16 insertions(+), 37 deletions(-)

diff --git a/pk/handlers.c b/pk/handlers.c
index 45b2317..8d71e4f 100644
--- a/pk/handlers.c
+++ b/pk/handlers.c
@@ -7,31 +7,19 @@
 #include "vm.h"
 
 int have_fp = 1; // initialized to 1 because it can't be in the .bss section!
-int have_vector = 1;
+int have_accelerator = 1;
   
-static void handle_vector_disabled(trapframe_t* tf)
+static void handle_accelerator_disabled(trapframe_t* tf)
 {
-  if (have_vector)
-    tf->sr |= SR_EV;
+  if (have_accelerator)
+    tf->sr |= SR_EA;
   else
   { 
     dump_tf(tf);
-    panic("No vector hardware!");
+    panic("No accelerator hardware!");
   }
 }
 
-static void handle_vector_bank(trapframe_t* tf)
-{
-  dump_tf(tf);
-  panic("Not enought banks were enabled to execute a vector instruction!");
-}
-
-static void handle_vector_illegal_instruction(trapframe_t* tf)
-{
-  dump_tf(tf);
-  panic("An illegal vector instruction was executed!");
-}
-
 static void handle_privileged_instruction(trapframe_t* tf)
 {
   dump_tf(tf);
@@ -152,9 +140,7 @@ void handle_trap(trapframe_t* tf)
     [CAUSE_MISALIGNED_STORE] = handle_misaligned_store,
     [CAUSE_FAULT_LOAD] = handle_fault_load,
     [CAUSE_FAULT_STORE] = handle_fault_store,
-    [CAUSE_VECTOR_DISABLED] = handle_vector_disabled,
-    [CAUSE_VECTOR_BANK] = handle_vector_bank,
-    [CAUSE_VECTOR_ILLEGAL_INSTRUCTION] = handle_vector_illegal_instruction,
+    [CAUSE_ACCELERATOR_DISABLED] = handle_accelerator_disabled,
   };
 
   kassert(tf->cause < ARRAY_SIZE(trap_handlers) && trap_handlers[tf->cause]);
diff --git a/pk/pcr.h b/pk/pcr.h
index 8c9617d..6c6d986 100644
--- a/pk/pcr.h
+++ b/pk/pcr.h
@@ -11,10 +11,10 @@
 #define SR_U64   0x00000020
 #define SR_S64   0x00000040
 #define SR_VM    0x00000080
-#define SR_EV    0x00000100
+#define SR_EA    0x00000100
 #define SR_IM    0x00FF0000
 #define SR_IP    0xFF000000
-#define SR_ZERO  ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP)
+#define SR_ZERO  ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
 #define SR_IM_SHIFT 16
 #define SR_IP_SHIFT 24
 
@@ -45,6 +45,9 @@
 #define IRQ_HOST  6
 #define IRQ_TIMER 7
 
+#define IMPL_SPIKE  1
+#define IMPL_ROCKET 2
+
 #define CAUSE_MISALIGNED_FETCH 0
 #define CAUSE_FAULT_FETCH 1
 #define CAUSE_ILLEGAL_INSTRUCTION 2
@@ -56,17 +59,7 @@
 #define CAUSE_MISALIGNED_STORE 9
 #define CAUSE_FAULT_LOAD 10
 #define CAUSE_FAULT_STORE 11
-#define CAUSE_VECTOR_DISABLED 12
-#define CAUSE_VECTOR_BANK 13
-
-#define CAUSE_VECTOR_MISALIGNED_FETCH 24
-#define CAUSE_VECTOR_FAULT_FETCH 25
-#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
-#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
-#define CAUSE_VECTOR_MISALIGNED_LOAD 28
-#define CAUSE_VECTOR_MISALIGNED_STORE 29
-#define CAUSE_VECTOR_FAULT_LOAD 30
-#define CAUSE_VECTOR_FAULT_STORE 31
+#define CAUSE_ACCELERATOR_DISABLED 12
 
 // page table entry (PTE) fields
 #define PTE_V    0x001 // Entry is a page Table descriptor
diff --git a/pk/pk.S b/pk/pk.S
index c9bb4b0..848a142 100644
--- a/pk/pk.S
+++ b/pk/pk.S
@@ -15,7 +15,7 @@ _start:
   mtpcr a0, evec
 
   li a0, SR_S | SR_PS | SR_EI | SR_S64
-  or a1, a0, SR_EF | SR_EV
+  or a1, a0, SR_EF | SR_EA
   mtpcr a1, status
   mfpcr a1, status
   mtpcr a0, status
@@ -24,9 +24,9 @@ _start:
   lui a0, %hi(have_fp)
   sw  a2, %lo(have_fp)(a0)
   
-  and a2, a1, SR_EV
-  lui a0, %hi(have_vector)
-  sw  a2, %lo(have_vector)(a0)
+  and a2, a1, SR_EA
+  lui a0, %hi(have_accelerator)
+  sw  a2, %lo(have_accelerator)(a0)
 
   lui a0, %hi(boot)
   jalr a0, %lo(boot)
-- 
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