From 410fb0384f0fac770ab89b675939790d9253bbf1 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sat, 25 Feb 2017 15:32:40 -0800
Subject: New counter-enable scheme

https://github.com/riscv/riscv-isa-manual/issues/10
---
 machine/emulation.c | 6 +++---
 machine/encoding.h  | 8 ++++----
 machine/minit.c     | 8 +++++---
 3 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/machine/emulation.c b/machine/emulation.c
index 696467d..25b39af 100644
--- a/machine/emulation.c
+++ b/machine/emulation.c
@@ -150,9 +150,9 @@ DECLARE_EMULATION_FUNC(truly_illegal_insn)
 
 static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result)
 {
-  uintptr_t counteren =
-    EXTRACT_FIELD(mstatus, MSTATUS_MPP) == PRV_U ? read_csr(mucounteren) :
-                                                   read_csr(mscounteren);
+  uintptr_t counteren = -1;
+  if (EXTRACT_FIELD(mstatus, MSTATUS_MPP) == PRV_U)
+    counteren = read_csr(scounteren);
 
   switch (num)
   {
diff --git a/machine/encoding.h b/machine/encoding.h
index e46e3d8..e8e9dd4 100644
--- a/machine/encoding.h
+++ b/machine/encoding.h
@@ -778,6 +778,7 @@
 #define CSR_SSTATUS 0x100
 #define CSR_SIE 0x104
 #define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
 #define CSR_SSCRATCH 0x140
 #define CSR_SEPC 0x141
 #define CSR_SCAUSE 0x142
@@ -790,6 +791,7 @@
 #define CSR_MIDELEG 0x303
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
 #define CSR_MSCRATCH 0x340
 #define CSR_MEPC 0x341
 #define CSR_MCAUSE 0x342
@@ -833,8 +835,6 @@
 #define CSR_MHPMCOUNTER29 0xb1d
 #define CSR_MHPMCOUNTER30 0xb1e
 #define CSR_MHPMCOUNTER31 0xb1f
-#define CSR_MUCOUNTEREN 0x320
-#define CSR_MSCOUNTEREN 0x321
 #define CSR_MHPMEVENT3 0x323
 #define CSR_MHPMEVENT4 0x324
 #define CSR_MHPMEVENT5 0x325
@@ -1248,6 +1248,7 @@ DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
 DECLARE_CSR(sstatus, CSR_SSTATUS)
 DECLARE_CSR(sie, CSR_SIE)
 DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
 DECLARE_CSR(sscratch, CSR_SSCRATCH)
 DECLARE_CSR(sepc, CSR_SEPC)
 DECLARE_CSR(scause, CSR_SCAUSE)
@@ -1260,6 +1261,7 @@ DECLARE_CSR(medeleg, CSR_MEDELEG)
 DECLARE_CSR(mideleg, CSR_MIDELEG)
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 DECLARE_CSR(mepc, CSR_MEPC)
 DECLARE_CSR(mcause, CSR_MCAUSE)
@@ -1303,8 +1305,6 @@ DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
-DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
-DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
diff --git a/machine/minit.c b/machine/minit.c
index 0a1e37e..9a3b01c 100644
--- a/machine/minit.c
+++ b/machine/minit.c
@@ -18,9 +18,11 @@ static void mstatus_init()
   write_csr(mstatus, MSTATUS_FS);
 
   // Enable user/supervisor use of perf counters
-  write_csr(mucounteren, -1);
-  write_csr(mscounteren, -1);
-  write_csr(mie, ~MIP_MTIP); // disable timer; enable other interrupts
+  write_csr(scounteren, -1);
+  write_csr(mcounteren, -1);
+
+  // Enable software interrupts
+  write_csr(mie, MIP_MSIP);
 
   // Disable paging
   write_csr(sptbr, 0);
-- 
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