diff options
author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-18 04:17:29 -0700 |
---|---|---|
committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-18 04:17:29 -0700 |
commit | 186ae3cc353fa3115d4ee0c9fcb18d8b2370c68c (patch) | |
tree | 3ecbf5e1e1333195e6f30764f876618fc79e829b /pk | |
parent | 2f7d5b9ee2ea937c6734650fecd9952e070a9795 (diff) | |
download | pk-186ae3cc353fa3115d4ee0c9fcb18d8b2370c68c.zip pk-186ae3cc353fa3115d4ee0c9fcb18d8b2370c68c.tar.gz pk-186ae3cc353fa3115d4ee0c9fcb18d8b2370c68c.tar.bz2 |
Renumber PCRs; refer to them with new ASM syntax
Diffstat (limited to 'pk')
-rw-r--r-- | pk/entry.S | 56 | ||||
-rw-r--r-- | pk/handlers.c | 22 | ||||
-rw-r--r-- | pk/pcr.h | 36 | ||||
-rw-r--r-- | pk/pk.S | 8 | ||||
-rw-r--r-- | pk/pk.h | 5 |
5 files changed, 64 insertions, 63 deletions
@@ -44,30 +44,24 @@ STORE x30,30*REGBYTES(x2) STORE x31,31*REGBYTES(x2) - mfpcr x3,ASM_CR(PCR_K0) - STORE x3,1*REGBYTES(x2) # x1 is in PCR_K0 - mfpcr x3,ASM_CR(PCR_K1) - STORE x3,2*REGBYTES(x2) # x2 is in PCR_K1 # get sr, epc, badvaddr, cause - mfpcr x3,ASM_CR(PCR_SR) # sr - STORE x3,32*REGBYTES(x2) - mfpcr x4,ASM_CR(PCR_EPC) # epc - STORE x4,33*REGBYTES(x2) - mfpcr x3,ASM_CR(PCR_BADVADDR) # badvaddr - STORE x3,34*REGBYTES(x2) - mfpcr x3,ASM_CR(PCR_CAUSE) # cause - STORE x3,35*REGBYTES(x2) + mfpcr x3,sup0 # x1 + mfpcr x4,sup1 # x2 + mfpcr x5,status + mfpcr x6,epc + mfpcr x7,badvaddr + mfpcr x8,cause + STORE x3,1*REGBYTES(x2) + STORE x4,2*REGBYTES(x2) + STORE x5,32*REGBYTES(x2) + STORE x6,33*REGBYTES(x2) + STORE x7,34*REGBYTES(x2) + STORE x8,35*REGBYTES(x2) # get faulting insn, if it wasn't a fetch-related trap - li x5, CAUSE_MISALIGNED_FETCH - li x6, CAUSE_FAULT_FETCH - beq x3, x5, 1f - beq x3, x6, 1f - lh x3,0(x4) - lh x4,2(x4) - sh x3, 36*REGBYTES(x2) - sh x4,2+36*REGBYTES(x2) + li x5,-1 + sd x5,36*REGBYTES(x2) 1: .endm @@ -79,9 +73,9 @@ pop_tf: # write the trap frame onto the stack LOAD a2,1*REGBYTES(a0) LOAD a3,2*REGBYTES(a0) - mtpcr a1,ASM_CR(PCR_SR) # restore sr (disable interrupts) - mtpcr a2,ASM_CR(PCR_K0) - mtpcr a3,ASM_CR(PCR_K1) + mtpcr a1,status # restore sr (disable interrupts) + mtpcr a2,sup0 + mtpcr a3,sup1 move x1,a0 LOAD x3,3*REGBYTES(x1) @@ -116,21 +110,21 @@ pop_tf: # write the trap frame onto the stack # gtfo! LOAD x2,33*REGBYTES(x1) - mtpcr x2,ASM_CR(PCR_EPC) - mfpcr x1,ASM_CR(PCR_K0) - mfpcr x2,ASM_CR(PCR_K1) + mfpcr x1,sup0 + mtpcr x2,epc + mfpcr x2,sup1 eret .global trap_entry trap_entry: - mtpcr ra,ASM_CR(PCR_K0) - mtpcr x2,ASM_CR(PCR_K1) + mtpcr x1,sup0 + mtpcr x2,sup1 # when coming from kernel, continue below its stack - mfpcr ra,ASM_CR(PCR_SR) - and ra,ra,SR_PS + mfpcr x1,status + and x1,x1,SR_PS add x2, sp, -320 - bnez ra, 1f + bnez x1, 1f la x2,stack_top-320 1:save_tf diff --git a/pk/handlers.c b/pk/handlers.c index d0ca7f5..45b2317 100644 --- a/pk/handlers.c +++ b/pk/handlers.c @@ -14,7 +14,10 @@ static void handle_vector_disabled(trapframe_t* tf) if (have_vector) tf->sr |= SR_EV; else - panic("No vector hardware! pc %lx, insn %x",tf->epc,(uint32_t)tf->insn); + { + dump_tf(tf); + panic("No vector hardware!"); + } } static void handle_vector_bank(trapframe_t* tf) @@ -37,17 +40,24 @@ static void handle_privileged_instruction(trapframe_t* tf) static void handle_illegal_instruction(trapframe_t* tf) { + tf->insn = *(uint16_t*)tf->epc; + int len = insn_len(tf->insn); + if (len == 4) + tf->insn |= ((uint32_t)*(uint16_t*)(tf->epc + 2) << 16); + else + kassert(len == 2); + #ifdef PK_ENABLE_FP_EMULATION - if(emulate_fp(tf) == 0) + if (emulate_fp(tf) == 0) { - advance_pc(tf); + tf->epc += len; return; } #endif - if(emulate_int(tf) == 0) + if (emulate_int(tf) == 0) { - advance_pc(tf); + tf->epc += len; return; } @@ -121,7 +131,7 @@ static void handle_syscall(trapframe_t* tf) tf->gpr[16] = ret.result; tf->gpr[21] = ret.err; - advance_pc(tf); + tf->epc += 4; } void handle_trap(trapframe_t* tf) @@ -18,28 +18,29 @@ #define SR_IM_SHIFT 16 #define SR_IP_SHIFT 24 -#define PCR_SR 0 -#define PCR_EPC 1 -#define PCR_BADVADDR 2 -#define PCR_EVEC 3 -#define PCR_CAUSE 4 -#define PCR_PTBR 5 -#define PCR_ASID 6 -#define PCR_FATC 7 -#define PCR_COUNT 8 -#define PCR_COMPARE 9 -#define PCR_SEND_IPI 10 -#define PCR_CLR_IPI 11 -#define PCR_HARTID 12 -#define PCR_IMPL 13 -#define PCR_K0 14 -#define PCR_K1 15 +#define PCR_SUP0 0 +#define PCR_SUP1 1 +#define PCR_EPC 2 +#define PCR_BADVADDR 3 +#define PCR_PTBR 4 +#define PCR_ASID 5 +#define PCR_COUNT 6 +#define PCR_COMPARE 7 +#define PCR_EVEC 8 +#define PCR_CAUSE 9 +#define PCR_SR 10 +#define PCR_HARTID 11 +#define PCR_IMPL 12 +#define PCR_FATC 13 +#define PCR_SEND_IPI 14 +#define PCR_CLR_IPI 15 #define PCR_VECBANK 18 #define PCR_VECCFG 19 #define PCR_RESET 29 #define PCR_TOHOST 30 #define PCR_FROMHOST 31 +#define IRQ_COP 2 #define IRQ_IPI 5 #define IRQ_HOST 6 #define IRQ_TIMER 7 @@ -91,9 +92,6 @@ #define RISCV_PGLEVEL_BITS 10 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) -#define ASM_CR(r) _ASM_CR(r) -#define _ASM_CR(r) cr##r - #ifndef __ASSEMBLER__ #define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \ @@ -12,13 +12,13 @@ _start: lui a0, %hi(trap_entry) add a0, a0, %lo(trap_entry) - mtpcr a0, ASM_CR(PCR_EVEC) + mtpcr a0, evec li a0, SR_S | SR_PS | SR_EI | SR_S64 or a1, a0, SR_EF | SR_EV - mtpcr a1, ASM_CR(PCR_SR) - mfpcr a1, ASM_CR(PCR_SR) - mtpcr a0, ASM_CR(PCR_SR) + mtpcr a1, status + mfpcr a1, status + mtpcr a0, status and a2, a1, SR_EF lui a0, %hi(have_fp) @@ -72,10 +72,9 @@ extern elf_info current; void load_elf(const char* fn, elf_info* info); -static inline void advance_pc(trapframe_t* tf) +static inline int insn_len(long insn) { - int rvc = (tf->insn & 0x3) < 0x3; - tf->epc += rvc ? 2 : 4; + return (insn & 0x3) < 0x3 ? 2 : 4; } #define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0])) |