[sim, pk, xcc, opcodes] great instruction renaming of 2011

4 files changed, 292 insertions, 288 deletions

diff --git a/pk/entry.S b/pk/entry.S
index d2fb72c..57acc69 100644
--- a/pk/entry.S
+++ b/pk/entry.S
@@ -1,12 +1,12 @@
 #include "pcr.h"
 
 #ifdef PK_ENABLE_KERNEL_64BIT
-# define STORE    sd
-# define LOAD     ld
+# define STORE    s.d
+# define LOAD     l.d
 # define REGBYTES 8
 #else
-# define STORE    sw
-# define LOAD     lw
+# define STORE    s.w
+# define LOAD     l.w
 # define REGBYTES 4
 #endif
 
@@ -62,7 +62,7 @@ save_tf:	# write the trap frame onto the stack
 
 	# get insn
 	and		$x4,$x4,~3
-	lw		$x3,0($x4)
+	l.w		$x3,0($x4)
 	STORE	$x3, 36*REGBYTES($x2)
 
 	ret
diff --git a/pk/fp.c b/pk/fp.c
index d9eb427..55e416d 100644
--- a/pk/fp.c
+++ b/pk/fp.c
@@ -61,22 +61,22 @@ int emulate_fp(trapframe_t* tf)
 
   #define IS_INSN(x) ((tf->insn & MASK_ ## x) == MATCH_ ## x)
 
-  if(IS_INSN(L_S))
+  if(IS_INSN(LF_W))
   {
     validate_address(tf, effective_address_load, 4, 0);
     set_fp_reg(RRD, 0, *(uint32_t*)effective_address_load);
   }
-  else if(IS_INSN(L_D))
+  else if(IS_INSN(LF_D))
   {
     validate_address(tf, effective_address_load, 8, 0);
     set_fp_reg(RRD, 1, *(uint64_t*)effective_address_load);
   }
-  else if(IS_INSN(S_S))
+  else if(IS_INSN(SF_W))
   {
     validate_address(tf, effective_address_store, 4, 1);
     *(uint32_t*)effective_address_store = frs2s;
   }
-  else if(IS_INSN(S_D))
+  else if(IS_INSN(SF_D))
   {
     validate_address(tf, effective_address_store, 8, 1);
     *(uint64_t*)effective_address_store = frs2d;
@@ -95,101 +95,101 @@ int emulate_fp(trapframe_t* tf)
     set_fp_reg(RRD, 1, XRS1);
   else if(IS_INSN(MTFLH_D))
     set_fp_reg(RRD, 1, (uint32_t)XRS1 | (XRS2 << 32));
-  else if(IS_INSN(SGNINJ_S))
+  else if(IS_INSN(FSINJ_S))
     set_fp_reg(RRD, 0, (frs1s &~ (uint32_t)INT32_MIN) | (frs2s & (uint32_t)INT32_MIN));
-  else if(IS_INSN(SGNINJ_D))
+  else if(IS_INSN(FSINJ_D))
     set_fp_reg(RRD, 1, (frs1d &~ INT64_MIN) | (frs2d & INT64_MIN));
-  else if(IS_INSN(SGNINJN_S))
+  else if(IS_INSN(FSINJN_S))
     set_fp_reg(RRD, 0, (frs1s &~ (uint32_t)INT32_MIN) | ((~frs2s) & (uint32_t)INT32_MIN));
-  else if(IS_INSN(SGNINJN_D))
+  else if(IS_INSN(FSINJN_D))
     set_fp_reg(RRD, 1, (frs1d &~ INT64_MIN) | ((~frs2d) & INT64_MIN));
-  else if(IS_INSN(SGNMUL_S))
+  else if(IS_INSN(FSMUL_S))
     set_fp_reg(RRD, 0, frs1s ^ (frs2s & (uint32_t)INT32_MIN));
-  else if(IS_INSN(SGNMUL_D))
+  else if(IS_INSN(FSMUL_D))
     set_fp_reg(RRD, 1, frs1d ^ (frs2d & INT64_MIN));
-  else if(IS_INSN(C_EQ_S))
+  else if(IS_INSN(FC_EQ_S))
     XRDR = f32_eq(frs1s, frs2s);
-  else if(IS_INSN(C_EQ_D))
+  else if(IS_INSN(FC_EQ_D))
     XRDR = f64_eq(frs1d, frs2d);
-  else if(IS_INSN(C_LE_S))
+  else if(IS_INSN(FC_LE_S))
     XRDR = f32_le(frs1s, frs2s);
-  else if(IS_INSN(C_LE_D))
+  else if(IS_INSN(FC_LE_D))
     XRDR = f64_le(frs1d, frs2d);
-  else if(IS_INSN(C_LT_S))
+  else if(IS_INSN(FC_LT_S))
     XRDR = f32_lt(frs1s, frs2s);
-  else if(IS_INSN(C_LT_D))
+  else if(IS_INSN(FC_LT_D))
     XRDR = f64_lt(frs1d, frs2d);
-  else if(IS_INSN(CVT_S_W))
+  else if(IS_INSN(FCVT_S_W))
     set_fp_reg(RRD, 0, i32_to_f32(XRS1));
-  else if(IS_INSN(CVT_S_L))
+  else if(IS_INSN(FCVT_S_L))
     set_fp_reg(RRD, 0, i64_to_f32(XRS1));
-  else if(IS_INSN(CVT_S_D))
+  else if(IS_INSN(FCVT_S_D))
     set_fp_reg(RRD, 0, f64_to_f32(frs1d));
-  else if(IS_INSN(CVT_D_W))
+  else if(IS_INSN(FCVT_D_W))
     set_fp_reg(RRD, 1, i32_to_f64(XRS1));
-  else if(IS_INSN(CVT_D_L))
+  else if(IS_INSN(FCVT_D_L))
     set_fp_reg(RRD, 1, i64_to_f64(XRS1));
-  else if(IS_INSN(CVT_D_S))
+  else if(IS_INSN(FCVT_D_S))
     set_fp_reg(RRD, 1, f32_to_f64(frs1s));
-  else if(IS_INSN(CVTU_S_W))
+  else if(IS_INSN(FCVTU_S_W))
     set_fp_reg(RRD, 0, ui32_to_f32(XRS1));
-  else if(IS_INSN(CVTU_S_L))
+  else if(IS_INSN(FCVTU_S_L))
     set_fp_reg(RRD, 0, ui64_to_f32(XRS1));
-  else if(IS_INSN(CVTU_D_W))
+  else if(IS_INSN(FCVTU_D_W))
     set_fp_reg(RRD, 1, ui32_to_f64(XRS1));
-  else if(IS_INSN(CVTU_D_L))
+  else if(IS_INSN(FCVTU_D_L))
     set_fp_reg(RRD, 1, ui64_to_f64(XRS1));
-  else if(IS_INSN(ADD_S))
+  else if(IS_INSN(FADD_S))
     set_fp_reg(RRD, 0, f32_add(frs1s, frs2s));
-  else if(IS_INSN(ADD_D))
+  else if(IS_INSN(FADD_D))
     set_fp_reg(RRD, 1, f64_add(frs1d, frs2d));
-  else if(IS_INSN(SUB_S))
+  else if(IS_INSN(FSUB_S))
     set_fp_reg(RRD, 0, f32_sub(frs1s, frs2s));
-  else if(IS_INSN(SUB_D))
+  else if(IS_INSN(FSUB_D))
     set_fp_reg(RRD, 1, f64_sub(frs1d, frs2d));
-  else if(IS_INSN(MUL_S))
+  else if(IS_INSN(FMUL_S))
     set_fp_reg(RRD, 0, f32_mul(frs1s, frs2s));
-  else if(IS_INSN(MUL_D))
+  else if(IS_INSN(FMUL_D))
     set_fp_reg(RRD, 1, f64_mul(frs1d, frs2d));
-  else if(IS_INSN(MADD_S))
+  else if(IS_INSN(FMADD_S))
     set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s));
-  else if(IS_INSN(MADD_D))
+  else if(IS_INSN(FMADD_D))
     set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d));
-  else if(IS_INSN(MSUB_S))
+  else if(IS_INSN(FMSUB_S))
     set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s ^ (uint32_t)INT32_MIN));
-  else if(IS_INSN(MSUB_D))
+  else if(IS_INSN(FMSUB_D))
     set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d ^ INT64_MIN));
-  else if(IS_INSN(NMADD_S))
+  else if(IS_INSN(FNMADD_S))
     set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s) ^ (uint32_t)INT32_MIN);
-  else if(IS_INSN(NMADD_D))
+  else if(IS_INSN(FNMADD_D))
     set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d) ^ INT64_MIN);
-  else if(IS_INSN(NMSUB_S))
+  else if(IS_INSN(FNMSUB_S))
     set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN);
-  else if(IS_INSN(NMSUB_D))
+  else if(IS_INSN(FNMSUB_D))
     set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d ^ INT64_MIN) ^ INT64_MIN);
-  else if(IS_INSN(DIV_S))
+  else if(IS_INSN(FDIV_S))
     set_fp_reg(RRD, 0, f32_div(frs1s, frs2s));
-  else if(IS_INSN(DIV_D))
+  else if(IS_INSN(FDIV_D))
     set_fp_reg(RRD, 1, f64_div(frs1d, frs2d));
-  else if(IS_INSN(SQRT_S))
+  else if(IS_INSN(FSQRT_S))
     set_fp_reg(RRD, 0, f32_sqrt(frs1s));
-  else if(IS_INSN(SQRT_D))
+  else if(IS_INSN(FSQRT_D))
     set_fp_reg(RRD, 1, f64_sqrt(frs1d));
-  else if(IS_INSN(CVT_W_S))
+  else if(IS_INSN(FCVT_W_S))
     XRDR = f32_to_i32_r_minMag(frs1s,true);
-  else if(IS_INSN(CVT_W_D))
+  else if(IS_INSN(FCVT_W_D))
     XRDR = f64_to_i32_r_minMag(frs1d,true);
-  else if(IS_INSN(CVT_L_S))
+  else if(IS_INSN(FCVT_L_S))
     XRDR = f32_to_i64_r_minMag(frs1s,true);
-  else if(IS_INSN(CVT_L_D))
+  else if(IS_INSN(FCVT_L_D))
     XRDR = f64_to_i64_r_minMag(frs1d,true);
-  else if(IS_INSN(CVTU_W_S))
+  else if(IS_INSN(FCVTU_W_S))
     XRDR = f32_to_ui32_r_minMag(frs1s,true);
-  else if(IS_INSN(CVTU_W_D))
+  else if(IS_INSN(FCVTU_W_D))
     XRDR = f64_to_ui32_r_minMag(frs1d,true);
-  else if(IS_INSN(CVTU_L_S))
+  else if(IS_INSN(FCVTU_L_S))
     XRDR = f32_to_ui64_r_minMag(frs1s,true);
-  else if(IS_INSN(CVTU_L_D))
+  else if(IS_INSN(FCVTU_L_D))
     XRDR = f64_to_ui64_r_minMag(frs1d,true);
   else
     return -1;
diff --git a/pk/fp_asm.S b/pk/fp_asm.S
index 21c54d9..81a81bf 100644
--- a/pk/fp_asm.S
+++ b/pk/fp_asm.S
@@ -7,38 +7,38 @@ get_fp_state:
 
 	mfcr	$v0, ASM_CR(CR_FSR)
 
-	s.d		$f0 ,  0($a0)
-	s.d		$f1 ,  8($a0)
-	s.d		$f2 , 16($a0)
-	s.d		$f3 , 24($a0)
-	s.d		$f4 , 32($a0)
-	s.d		$f5 , 40($a0)
-	s.d		$f6 , 48($a0)
-	s.d		$f7 , 56($a0)
-	s.d		$f8 , 64($a0)
-	s.d		$f9 , 72($a0)
-	s.d		$f10, 80($a0)
-	s.d		$f11, 88($a0)
-	s.d		$f12, 96($a0)
-	s.d		$f13,104($a0)
-	s.d		$f14,112($a0)
-	s.d		$f15,120($a0)
-	s.d		$f16,128($a0)
-	s.d		$f17,136($a0)
-	s.d		$f18,144($a0)
-	s.d		$f19,152($a0)
-	s.d		$f20,160($a0)
-	s.d		$f21,168($a0)
-	s.d		$f22,176($a0)
-	s.d		$f23,184($a0)
-	s.d		$f24,192($a0)
-	s.d		$f25,200($a0)
-	s.d		$f26,208($a0)
-	s.d		$f27,216($a0)
-	s.d		$f28,224($a0)
-	s.d		$f29,232($a0)
-	s.d		$f30,240($a0)
-	s.d		$f31,248($a0)
+	sf.d		$f0 ,  0($a0)
+	sf.d		$f1 ,  8($a0)
+	sf.d		$f2 , 16($a0)
+	sf.d		$f3 , 24($a0)
+	sf.d		$f4 , 32($a0)
+	sf.d		$f5 , 40($a0)
+	sf.d		$f6 , 48($a0)
+	sf.d		$f7 , 56($a0)
+	sf.d		$f8 , 64($a0)
+	sf.d		$f9 , 72($a0)
+	sf.d		$f10, 80($a0)
+	sf.d		$f11, 88($a0)
+	sf.d		$f12, 96($a0)
+	sf.d		$f13,104($a0)
+	sf.d		$f14,112($a0)
+	sf.d		$f15,120($a0)
+	sf.d		$f16,128($a0)
+	sf.d		$f17,136($a0)
+	sf.d		$f18,144($a0)
+	sf.d		$f19,152($a0)
+	sf.d		$f20,160($a0)
+	sf.d		$f21,168($a0)
+	sf.d		$f22,176($a0)
+	sf.d		$f23,184($a0)
+	sf.d		$f24,192($a0)
+	sf.d		$f25,200($a0)
+	sf.d		$f26,208($a0)
+	sf.d		$f27,216($a0)
+	sf.d		$f28,224($a0)
+	sf.d		$f29,232($a0)
+	sf.d		$f30,240($a0)
+	sf.d		$f31,248($a0)
 
 	ret
 
@@ -48,38 +48,38 @@ get_fp_state:
 	.ent	put_fp_state
 put_fp_state:
 
-	l.d		$f0 ,  0($a0)
-	l.d		$f1 ,  8($a0)
-	l.d		$f2 , 16($a0)
-	l.d		$f3 , 24($a0)
-	l.d		$f4 , 32($a0)
-	l.d		$f5 , 40($a0)
-	l.d		$f6 , 48($a0)
-	l.d		$f7 , 56($a0)
-	l.d		$f8 , 64($a0)
-	l.d		$f9 , 72($a0)
-	l.d		$f10, 80($a0)
-	l.d		$f11, 88($a0)
-	l.d		$f12, 96($a0)
-	l.d		$f13,104($a0)
-	l.d		$f14,112($a0)
-	l.d		$f15,120($a0)
-	l.d		$f16,128($a0)
-	l.d		$f17,136($a0)
-	l.d		$f18,144($a0)
-	l.d		$f19,152($a0)
-	l.d		$f20,160($a0)
-	l.d		$f21,168($a0)
-	l.d		$f22,176($a0)
-	l.d		$f23,184($a0)
-	l.d		$f24,192($a0)
-	l.d		$f25,200($a0)
-	l.d		$f26,208($a0)
-	l.d		$f27,216($a0)
-	l.d		$f28,224($a0)
-	l.d		$f29,232($a0)
-	l.d		$f30,240($a0)
-	l.d		$f31,248($a0)
+	lf.d		$f0 ,  0($a0)
+	lf.d		$f1 ,  8($a0)
+	lf.d		$f2 , 16($a0)
+	lf.d		$f3 , 24($a0)
+	lf.d		$f4 , 32($a0)
+	lf.d		$f5 , 40($a0)
+	lf.d		$f6 , 48($a0)
+	lf.d		$f7 , 56($a0)
+	lf.d		$f8 , 64($a0)
+	lf.d		$f9 , 72($a0)
+	lf.d		$f10, 80($a0)
+	lf.d		$f11, 88($a0)
+	lf.d		$f12, 96($a0)
+	lf.d		$f13,104($a0)
+	lf.d		$f14,112($a0)
+	lf.d		$f15,120($a0)
+	lf.d		$f16,128($a0)
+	lf.d		$f17,136($a0)
+	lf.d		$f18,144($a0)
+	lf.d		$f19,152($a0)
+	lf.d		$f20,160($a0)
+	lf.d		$f21,168($a0)
+	lf.d		$f22,176($a0)
+	lf.d		$f23,184($a0)
+	lf.d		$f24,192($a0)
+	lf.d		$f25,200($a0)
+	lf.d		$f26,208($a0)
+	lf.d		$f27,216($a0)
+	lf.d		$f28,224($a0)
+	lf.d		$f29,232($a0)
+	lf.d		$f30,240($a0)
+	lf.d		$f31,248($a0)
 
 	mtcr	$a1, ASM_CR(CR_FSR)
 
diff --git a/pk/riscv-opc.h b/pk/riscv-opc.h
index 57e9b97..3bbbb61 100644
--- a/pk/riscv-opc.h
+++ b/pk/riscv-opc.h
@@ -1,112 +1,100 @@
 /* Automatically generated by parse-opcodes */
-#define MATCH_CVT_W_D 0xa1ea
-#define  MASK_CVT_W_D 0x3ff1ff
 #define MATCH_MFF_D 0x185ea
 #define  MASK_MFF_D 0x7c1ffff
-#define MATCH_SGNINJ_D 0x51ea
-#define  MASK_SGNINJ_D 0x1ffff
-#define MATCH_AMO_ADD 0x1fa
-#define  MASK_AMO_ADD 0x1ffff
+#define MATCH_FSINJN_D 0x61ea
+#define  MASK_FSINJN_D 0x1ffff
 #define MATCH_REMUW 0x1cf7
 #define  MASK_REMUW 0x1ffff
-#define MATCH_NMADD_S 0x6f
-#define  MASK_NMADD_S 0x1ff
 #define MATCH_BLTU 0x363
 #define  MASK_BLTU 0x3ff
-#define MATCH_C_EQ_S 0x1506a
-#define  MASK_C_EQ_S 0x1ffff
-#define MATCH_SGNINJ_S 0x506a
-#define  MASK_SGNINJ_S 0x1ffff
-#define MATCH_DIV_D 0x31ea
-#define  MASK_DIV_D 0x1f1ff
-#define MATCH_CVT_W_S 0xa06a
-#define  MASK_CVT_W_S 0x3ff1ff
-#define MATCH_CVT_S_W 0xe06a
-#define  MASK_CVT_S_W 0x3ff1ff
-#define MATCH_NMADD_D 0x1ef
-#define  MASK_NMADD_D 0x1ff
-#define MATCH_C_EQ_D 0x151ea
-#define  MASK_C_EQ_D 0x1ffff
+#define MATCH_FSINJN_S 0x606a
+#define  MASK_FSINJN_S 0x1ffff
+#define MATCH_MFF_S 0x1846a
+#define  MASK_MFF_S 0x7c1ffff
 #define MATCH_SLLIW 0x7f6
 #define  MASK_SLLIW 0x20ffff
-#define MATCH_AMOW_MAX 0x157a
-#define  MASK_AMOW_MAX 0x1ffff
-#define MATCH_CVTU_D_L 0xd1ea
-#define  MASK_CVTU_D_L 0x3ff1ff
-#define MATCH_LH 0xf8
-#define  MASK_LH 0x3ff
-#define MATCH_LW 0x178
-#define  MASK_LW 0x3ff
+#define MATCH_FCVT_D_L 0xc1ea
+#define  MASK_FCVT_D_L 0x3ff1ff
+#define MATCH_FCVT_D_W 0xe1ea
+#define  MASK_FCVT_D_W 0x3fffff
 #define MATCH_ADD 0x75
 #define  MASK_ADD 0x1ffff
-#define MATCH_AMOW_AND 0x97a
-#define  MASK_AMOW_AND 0x1ffff
+#define MATCH_FCVT_D_S 0x101ea
+#define  MASK_FCVT_D_S 0x3fffff
+#define MATCH_LF_D 0x1e8
+#define  MASK_LF_D 0x3ff
 #define MATCH_MFPCR 0xeb
 #define  MASK_MFPCR 0x7c1ffff
-#define MATCH_CVTU_D_W 0xf1ea
-#define  MASK_CVTU_D_W 0x3fffff
 #define MATCH_BNE 0xe3
 #define  MASK_BNE 0x3ff
 #define MATCH_MTPCR 0x4eb
 #define  MASK_MTPCR 0xf801ffff
-#define MATCH_ADD_S 0x6a
-#define  MASK_ADD_S 0x1f1ff
+#define MATCH_FCVT_S_D 0x1306a
+#define  MASK_FCVT_S_D 0x3ff1ff
 #define MATCH_BGEU 0x3e3
 #define  MASK_BGEU 0x3ff
-#define MATCH_CVTU_L_D 0x91ea
-#define  MASK_CVTU_L_D 0x3ff1ff
 #define MATCH_DI 0x46b
 #define  MASK_DI 0x7ffffff
 #define MATCH_SLTIU 0x1f4
 #define  MASK_SLTIU 0x3ff
 #define MATCH_MFFL_D 0x195ea
 #define  MASK_MFFL_D 0x7c1ffff
-#define MATCH_SGNMUL_D 0x71ea
-#define  MASK_SGNMUL_D 0x1ffff
-#define MATCH_CVTU_L_S 0x906a
-#define  MASK_CVTU_L_S 0x3ff1ff
-#define MATCH_ADD_D 0x1ea
-#define  MASK_ADD_D 0x1f1ff
+#define MATCH_FADD_S 0x6a
+#define  MASK_FADD_S 0x1f1ff
+#define MATCH_FCVT_S_W 0xe06a
+#define  MASK_FCVT_S_W 0x3ff1ff
 #define MATCH_MUL 0xf5
 #define  MASK_MUL 0x1ffff
-#define MATCH_AMOW_MIN 0x117a
-#define  MASK_AMOW_MIN 0x1ffff
-#define MATCH_NMSUB_D 0x1ee
-#define  MASK_NMSUB_D 0x1ff
-#define MATCH_AMO_SWAP 0x5fa
-#define  MASK_AMO_SWAP 0x1ffff
+#define MATCH_AMOMINU_D 0x19fa
+#define  MASK_AMOMINU_D 0x1ffff
+#define MATCH_FSEL_S 0x67
+#define  MASK_FSEL_S 0xfff
 #define MATCH_SRLI 0xbf4
 #define  MASK_SRLI 0xffff
+#define MATCH_FCVTU_W_S 0xb06a
+#define  MASK_FCVTU_W_S 0x3ff1ff
+#define MATCH_AMOMINU_W 0x197a
+#define  MASK_AMOMINU_W 0x1ffff
 #define MATCH_DIVUW 0x14f7
 #define  MASK_DIVUW 0x1ffff
 #define MATCH_MFFH_D 0x1a5ea
 #define  MASK_MFFH_D 0x7c1ffff
 #define MATCH_SRLW 0xbf7
 #define  MASK_SRLW 0x1ffff
-#define MATCH_NMSUB_S 0x6e
-#define  MASK_NMSUB_S 0x1ff
 #define MATCH_MFCR 0xfb
 #define  MASK_MFCR 0x7c1ffff
-#define MATCH_C_LE_D 0x171ea
-#define  MASK_C_LE_D 0x1ffff
 #define MATCH_DIV 0x10f5
 #define  MASK_DIV 0x1ffff
-#define MATCH_MFF_S 0x1846a
-#define  MASK_MFF_S 0x7c1ffff
-#define MATCH_AMOW_OR 0xd7a
-#define  MASK_AMOW_OR 0x1ffff
-#define MATCH_EI 0x6b
-#define  MASK_EI 0x7ffffff
+#define MATCH_FSEL_D 0x1e7
+#define  MASK_FSEL_D 0xfff
+#define MATCH_S_D 0x1f9
+#define  MASK_S_D 0x3ff
+#define MATCH_J 0x60
+#define  MASK_J 0x7f
+#define MATCH_S_B 0x79
+#define  MASK_S_B 0x3ff
+#define MATCH_FNMSUB_S 0x6e
+#define  MASK_FNMSUB_S 0x1ff
+#define MATCH_FCVT_L_S 0x806a
+#define  MASK_FCVT_L_S 0x3ff1ff
 #define MATCH_SYNC 0x17b
 #define  MASK_SYNC 0xffffffff
+#define MATCH_S_H 0xf9
+#define  MASK_S_H 0x3ff
 #define MATCH_MTF_S 0x1c46a
 #define  MASK_MTF_S 0x3fffff
-#define MATCH_S_S 0x169
-#define  MASK_S_S 0x3ff
+#define MATCH_S_W 0x179
+#define  MASK_S_W 0x3ff
+#define MATCH_FDIV_S 0x306a
+#define  MASK_FDIV_S 0x1f1ff
+#define MATCH_SF_D 0x1e9
+#define  MASK_SF_D 0x3ff
 #define MATCH_MTCR 0x4fb
 #define  MASK_MTCR 0xf801ffff
-#define MATCH_MSUB_S 0x6d
-#define  MASK_MSUB_S 0x1ff
+#define MATCH_FCVT_L_D 0x81ea
+#define  MASK_FCVT_L_D 0x3ff1ff
+#define MATCH_FNMSUB_D 0x1ee
+#define  MASK_FNMSUB_D 0x1ff
 #define MATCH_ADDW 0x77
 #define  MASK_ADDW 0x1ffff
 #define MATCH_SLTU 0xc75
@@ -117,94 +105,118 @@
 #define  MASK_SUB 0x1ffff
 #define MATCH_ERET 0x16b
 #define  MASK_ERET 0xffffffff
+#define MATCH_FCVTU_D_W 0xf1ea
+#define  MASK_FCVTU_D_W 0x3fffff
 #define MATCH_BLT 0x263
 #define  MASK_BLT 0x3ff
-#define MATCH_SGNINJN_D 0x61ea
-#define  MASK_SGNINJN_D 0x1ffff
+#define MATCH_FC_LT_S 0x1606a
+#define  MASK_FC_LT_S 0x1ffff
 #define MATCH_REM 0x18f5
 #define  MASK_REM 0x1ffff
 #define MATCH_SRLIW 0xbf6
 #define  MASK_SRLIW 0x20ffff
 #define MATCH_LUI 0x71
 #define  MASK_LUI 0x7f
+#define MATCH_L_W 0x178
+#define  MASK_L_W 0x3ff
 #define MATCH_ADDI 0x74
 #define  MASK_ADDI 0x3ff
+#define MATCH_FC_LT_D 0x161ea
+#define  MASK_FC_LT_D 0x1ffff
 #define MATCH_MULH 0x8f5
 #define  MASK_MULH 0x1ffff
-#define MATCH_SGNINJN_S 0x606a
-#define  MASK_SGNINJN_S 0x1ffff
+#define MATCH_FMUL_S 0x206a
+#define  MASK_FMUL_S 0x1f1ff
 #define MATCH_SRAI 0xff4
 #define  MASK_SRAI 0xffff
+#define MATCH_AMOAND_D 0x9fa
+#define  MASK_AMOAND_D 0x1ffff
 #define MATCH_SRAW 0xff7
 #define  MASK_SRAW 0x1ffff
-#define MATCH_LD 0x1f8
-#define  MASK_LD 0x3ff
+#define MATCH_FMUL_D 0x21ea
+#define  MASK_FMUL_D 0x1f1ff
 #define MATCH_ORI 0x2f4
 #define  MASK_ORI 0x3ff
-#define MATCH_LB 0x78
-#define  MASK_LB 0x3ff
 #define MATCH_ADDIW 0x76
 #define  MASK_ADDIW 0x3ff
-#define MATCH_MULW 0xf7
-#define  MASK_MULW 0x1ffff
+#define MATCH_AMOAND_W 0x97a
+#define  MASK_AMOAND_W 0x1ffff
 #define MATCH_MTFLH_D 0x1c7ea
 #define  MASK_MTFLH_D 0x1ffff
 #define MATCH_SRA 0xff5
 #define  MASK_SRA 0x1ffff
-#define MATCH_BGE 0x2e3
-#define  MASK_BGE 0x3ff
-#define MATCH_CVT_L_D 0x81ea
-#define  MASK_CVT_L_D 0x3ff1ff
+#define MATCH_L_BU 0x278
+#define  MASK_L_BU 0x3ff
 #define MATCH_SRAIW 0xff6
 #define  MASK_SRAIW 0x20ffff
 #define MATCH_SRL 0xbf5
 #define  MASK_SRL 0x1ffff
-#define MATCH_CVT_L_S 0x806a
-#define  MASK_CVT_L_S 0x3ff1ff
+#define MATCH_FC_EQ_D 0x151ea
+#define  MASK_FC_EQ_D 0x1ffff
 #define MATCH_OR 0x1475
 #define  MASK_OR 0x1ffff
+#define MATCH_FMADD_D 0x1ec
+#define  MASK_FMADD_D 0x1ff
 #define MATCH_SUBW 0x477
 #define  MASK_SUBW 0x1ffff
 #define MATCH_JALR_C 0x62
 #define  MASK_JALR_C 0x3ff
-#define MATCH_CVTU_S_W 0xf06a
-#define  MASK_CVTU_S_W 0x3ff1ff
-#define MATCH_AMOW_MINU 0x197a
-#define  MASK_AMOW_MINU 0x1ffff
+#define MATCH_LF_W 0x168
+#define  MASK_LF_W 0x3ff
+#define MATCH_AMOMAXU_D 0x1dfa
+#define  MASK_AMOMAXU_D 0x1ffff
+#define MATCH_SF_W 0x169
+#define  MASK_SF_W 0x3ff
 #define MATCH_JALR_J 0x162
 #define  MASK_JALR_J 0x3ff
-#define MATCH_S_D 0x1e9
-#define  MASK_S_D 0x3ff
-#define MATCH_AMO_OR 0xdfa
-#define  MASK_AMO_OR 0x1ffff
 #define MATCH_XORI 0x374
 #define  MASK_XORI 0x3ff
 #define MATCH_JALR_R 0xe2
 #define  MASK_JALR_R 0x3ff
-#define MATCH_CVTU_S_L 0xd06a
-#define  MASK_CVTU_S_L 0x3ff1ff
-#define MATCH_AMO_MAX 0x15fa
-#define  MASK_AMO_MAX 0x1ffff
-#define MATCH_AMO_MIN 0x11fa
-#define  MASK_AMO_MIN 0x1ffff
+#define MATCH_AMOMAXU_W 0x1d7a
+#define  MASK_AMOMAXU_W 0x1ffff
+#define MATCH_AMOMIN_D 0x11fa
+#define  MASK_AMOMIN_D 0x1ffff
+#define MATCH_EI 0x6b
+#define  MASK_EI 0x7ffffff
+#define MATCH_FSMUL_S 0x706a
+#define  MASK_FSMUL_S 0x1ffff
 #define MATCH_ANDI 0x274
 #define  MASK_ANDI 0x3ff
+#define MATCH_FNMADD_S 0x6f
+#define  MASK_FNMADD_S 0x1ff
 #define MATCH_JAL 0x61
 #define  MASK_JAL 0x7f
-#define MATCH_LWU 0x378
-#define  MASK_LWU 0x3ff
-#define MATCH_AMO_MINU 0x19fa
-#define  MASK_AMO_MINU 0x1ffff
-#define MATCH_MSUB_D 0x1ed
-#define  MASK_MSUB_D 0x1ff
-#define MATCH_SUB_S 0x106a
-#define  MASK_SUB_S 0x1f1ff
+#define MATCH_MULW 0xf7
+#define  MASK_MULW 0x1ffff
+#define MATCH_FSMUL_D 0x71ea
+#define  MASK_FSMUL_D 0x1ffff
+#define MATCH_FNMADD_D 0x1ef
+#define  MASK_FNMADD_D 0x1ff
+#define MATCH_AMOADD_D 0x1fa
+#define  MASK_AMOADD_D 0x1ffff
+#define MATCH_FSINJ_D 0x51ea
+#define  MASK_FSINJ_D 0x1ffff
+#define MATCH_AMOMAX_W 0x157a
+#define  MASK_AMOMAX_W 0x1ffff
+#define MATCH_FCVT_W_S 0xa06a
+#define  MASK_FCVT_W_S 0x3ff1ff
+#define MATCH_AMOADD_W 0x17a
+#define  MASK_AMOADD_W 0x1ffff
+#define MATCH_FSINJ_S 0x506a
+#define  MASK_FSINJ_S 0x1ffff
+#define MATCH_AMOMAX_D 0x15fa
+#define  MASK_AMOMAX_D 0x1ffff
+#define MATCH_FCVT_W_D 0xa1ea
+#define  MASK_FCVT_W_D 0x3ff1ff
+#define MATCH_BGE 0x2e3
+#define  MASK_BGE 0x3ff
 #define MATCH_SLT 0x875
 #define  MASK_SLT 0x1ffff
 #define MATCH_SLLW 0x7f7
 #define  MASK_SLLW 0x1ffff
-#define MATCH_J 0x60
-#define  MASK_J 0x7f
+#define MATCH_AMOOR_D 0xdfa
+#define  MASK_AMOOR_D 0x1ffff
 #define MATCH_SLTI 0x174
 #define  MASK_SLTI 0x3ff
 #define MATCH_REMU 0x1cf5
@@ -213,89 +225,81 @@
 #define  MASK_REMW 0x1ffff
 #define MATCH_SLL 0x7f5
 #define  MASK_SLL 0x1ffff
+#define MATCH_L_HU 0x2f8
+#define  MASK_L_HU 0x3ff
 #define MATCH_SLLI 0x7f4
 #define  MASK_SLLI 0xffff
-#define MATCH_SUB_D 0x11ea
-#define  MASK_SUB_D 0x1f1ff
+#define MATCH_AMOOR_W 0xd7a
+#define  MASK_AMOOR_W 0x1ffff
 #define MATCH_BEQ 0x63
 #define  MASK_BEQ 0x3ff
+#define MATCH_FSUB_S 0x106a
+#define  MASK_FSUB_S 0x1f1ff
 #define MATCH_AND 0x1075
 #define  MASK_AND 0x1ffff
-#define MATCH_LBU 0x278
-#define  MASK_LBU 0x3ff
-#define MATCH_SQRT_S 0x406a
-#define  MASK_SQRT_S 0x3ff1ff
+#define MATCH_FC_LE_S 0x1706a
+#define  MASK_FC_LE_S 0x1ffff
 #define MATCH_SYSCALL 0x1fb
 #define  MASK_SYSCALL 0xffc003ff
-#define MATCH_C_LT_S 0x1606a
-#define  MASK_C_LT_S 0x1ffff
+#define MATCH_FCVTU_S_W 0xf06a
+#define  MASK_FCVTU_S_W 0x3ff1ff
 #define MATCH_MTF_D 0x1c5ea
 #define  MASK_MTF_D 0x3fffff
-#define MATCH_SQRT_D 0x41ea
-#define  MASK_SQRT_D 0x3ff1ff
-#define MATCH_AMOW_ADD 0x17a
-#define  MASK_AMOW_ADD 0x1ffff
-#define MATCH_MADD_S 0x6c
-#define  MASK_MADD_S 0x1ff
+#define MATCH_FC_LE_D 0x171ea
+#define  MASK_FC_LE_D 0x1ffff
+#define MATCH_FCVTU_S_L 0xd06a
+#define  MASK_FCVTU_S_L 0x3ff1ff
 #define MATCH_MULHU 0xcf5
 #define  MASK_MULHU 0x1ffff
-#define MATCH_AMO_AND 0x9fa
-#define  MASK_AMO_AND 0x1ffff
-#define MATCH_SGNMUL_S 0x706a
-#define  MASK_SGNMUL_S 0x1ffff
+#define MATCH_FCVTU_W_D 0xb1ea
+#define  MASK_FCVTU_W_D 0x3ff1ff
+#define MATCH_FCVTU_L_S 0x906a
+#define  MASK_FCVTU_L_S 0x3ff1ff
+#define MATCH_FADD_D 0x1ea
+#define  MASK_FADD_D 0x1f1ff
 #define MATCH_RDNPC 0x7b
 #define  MASK_RDNPC 0x7ffffff
-#define MATCH_CVT_S_L 0xc06a
-#define  MASK_CVT_S_L 0x3ff1ff
-#define MATCH_MADD_D 0x1ec
-#define  MASK_MADD_D 0x1ff
+#define MATCH_FCVT_S_L 0xc06a
+#define  MASK_FCVT_S_L 0x3ff1ff
 #define MATCH_SYNCI 0x3f8
 #define  MASK_SYNCI 0xf80003ff
-#define MATCH_DIV_S 0x306a
-#define  MASK_DIV_S 0x1f1ff
 #define MATCH_UNIMP 0x0
 #define  MASK_UNIMP 0xffffffff
-#define MATCH_CVT_S_D 0x1306a
-#define  MASK_CVT_S_D 0x3ff1ff
-#define MATCH_C_LE_S 0x1706a
-#define  MASK_C_LE_S 0x1ffff
-#define MATCH_MUL_S 0x206a
-#define  MASK_MUL_S 0x1f1ff
-#define MATCH_CVT_D_S 0x101ea
-#define  MASK_CVT_D_S 0x3fffff
-#define MATCH_CVT_D_W 0xe1ea
-#define  MASK_CVT_D_W 0x3fffff
-#define MATCH_L_S 0x168
-#define  MASK_L_S 0x3ff
-#define MATCH_CVT_D_L 0xc1ea
-#define  MASK_CVT_D_L 0x3ff1ff
+#define MATCH_FCVTU_L_D 0x91ea
+#define  MASK_FCVTU_L_D 0x3ff1ff
+#define MATCH_FSUB_D 0x11ea
+#define  MASK_FSUB_D 0x1f1ff
+#define MATCH_FMADD_S 0x6c
+#define  MASK_FMADD_S 0x1ff
+#define MATCH_FSQRT_S 0x406a
+#define  MASK_FSQRT_S 0x3ff1ff
+#define MATCH_AMOMIN_W 0x117a
+#define  MASK_AMOMIN_W 0x1ffff
+#define MATCH_AMOSWAP_D 0x5fa
+#define  MASK_AMOSWAP_D 0x1ffff
+#define MATCH_FSQRT_D 0x41ea
+#define  MASK_FSQRT_D 0x3ff1ff
+#define MATCH_FC_EQ_S 0x1506a
+#define  MASK_FC_EQ_S 0x1ffff
+#define MATCH_FDIV_D 0x31ea
+#define  MASK_FDIV_D 0x1f1ff
+#define MATCH_L_H 0xf8
+#define  MASK_L_H 0x3ff
 #define MATCH_DIVW 0x10f7
 #define  MASK_DIVW 0x1ffff
-#define MATCH_L_D 0x1e8
+#define MATCH_L_D 0x1f8
 #define  MASK_L_D 0x3ff
 #define MATCH_DIVU 0x14f5
 #define  MASK_DIVU 0x1ffff
-#define MATCH_MUL_D 0x21ea
-#define  MASK_MUL_D 0x1f1ff
-#define MATCH_CVTU_W_S 0xb06a
-#define  MASK_CVTU_W_S 0x3ff1ff
-#define MATCH_SW 0x179
-#define  MASK_SW 0x3ff
-#define MATCH_AMOW_SWAP 0x57a
-#define  MASK_AMOW_SWAP 0x1ffff
-#define MATCH_CVTU_W_D 0xb1ea
-#define  MASK_CVTU_W_D 0x3ff1ff
-#define MATCH_LHU 0x2f8
-#define  MASK_LHU 0x3ff
-#define MATCH_SH 0xf9
-#define  MASK_SH 0x3ff
-#define MATCH_AMO_MAXU 0x1dfa
-#define  MASK_AMO_MAXU 0x1ffff
-#define MATCH_AMOW_MAXU 0x1d7a
-#define  MASK_AMOW_MAXU 0x1ffff
-#define MATCH_SB 0x79
-#define  MASK_SB 0x3ff
-#define MATCH_C_LT_D 0x161ea
-#define  MASK_C_LT_D 0x1ffff
-#define MATCH_SD 0x1f9
-#define  MASK_SD 0x3ff
+#define MATCH_AMOSWAP_W 0x57a
+#define  MASK_AMOSWAP_W 0x1ffff
+#define MATCH_FCVTU_D_L 0xd1ea
+#define  MASK_FCVTU_D_L 0x3ff1ff
+#define MATCH_L_B 0x78
+#define  MASK_L_B 0x3ff
+#define MATCH_L_WU 0x378
+#define  MASK_L_WU 0x3ff
+#define MATCH_FMSUB_S 0x6d
+#define  MASK_FMSUB_S 0x1ff
+#define MATCH_FMSUB_D 0x1ed
+#define  MASK_FMSUB_D 0x1ff