Revert "Enable support for the four custom instructions"

This reverts commit 2fa1726f0ebbe5911cd12c27c42881f17ec43114.

Refactoring support for custom instructions.

1 files changed, 0 insertions, 72 deletions

diff --git a/pk/encoding.h b/pk/encoding.h
index 77d35c8..089a8a9 100644
--- a/pk/encoding.h
+++ b/pk/encoding.h
@@ -99,8 +99,6 @@
 #define RISCV_ENCODING_H
 #define MATCH_FMV_S_X 0xf0000053
 #define MASK_FMV_S_X  0xfff0707f
-#define MATCH_CUSTOM1_RS1 0x202b
-#define MASK_CUSTOM1_RS1  0x707f
 #define MATCH_AMOXOR_W 0x2000202f
 #define MASK_AMOXOR_W  0xf800707f
 #define MATCH_REMUW 0x200703b
@@ -115,16 +113,12 @@
 #define MASK_FSGNJN_D  0xfe00707f
 #define MATCH_FMIN_S 0x28000053
 #define MASK_FMIN_S  0xfe00707f
-#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
 #define MATCH_CSRRW 0x1073
 #define MASK_CSRRW  0x707f
 #define MATCH_SLLIW 0x101b
 #define MASK_SLLIW  0xfe00707f
 #define MATCH_LB 0x3
 #define MASK_LB  0x707f
-#define MATCH_CUSTOM1_RD 0x402b
-#define MASK_CUSTOM1_RD  0x707f
 #define MATCH_FMAX_S 0x28001053
 #define MASK_FMAX_S  0xfe00707f
 #define MATCH_LH 0x1003
@@ -177,8 +171,6 @@
 #define MASK_FDIV_D  0xfe00007f
 #define MATCH_FENCE 0xf
 #define MASK_FENCE  0x707f
-#define MATCH_CUSTOM0_RS1_RS2 0x300b
-#define MASK_CUSTOM0_RS1_RS2  0x707f
 #define MATCH_FNMSUB_S 0x4b
 #define MASK_FNMSUB_S  0x600007f
 #define MATCH_FCVT_L_S 0xc0200053
@@ -207,8 +199,6 @@
 #define MASK_BLT  0x707f
 #define MATCH_SCALL 0x73
 #define MASK_SCALL  0xffffffff
-#define MATCH_CUSTOM2_RD_RS1 0x605b
-#define MASK_CUSTOM2_RD_RS1  0x707f
 #define MATCH_FCLASS_S 0xe0001053
 #define MASK_FCLASS_S  0xfff0707f
 #define MATCH_SC_W 0x1800202f
@@ -263,18 +253,12 @@
 #define MASK_SRAIW  0xfe00707f
 #define MATCH_SRL 0x5033
 #define MASK_SRL  0xfe00707f
-#define MATCH_CUSTOM3_RS1 0x207b
-#define MASK_CUSTOM3_RS1  0x707f
 #define MATCH_FSUB_D 0xa000053
 #define MASK_FSUB_D  0xfe00007f
-#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
 #define MATCH_FSGNJX_S 0x20002053
 #define MASK_FSGNJX_S  0xfe00707f
 #define MATCH_FEQ_D 0xa2002053
 #define MASK_FEQ_D  0xfe00707f
-#define MATCH_CUSTOM1_RD_RS1 0x602b
-#define MASK_CUSTOM1_RD_RS1  0x707f
 #define MATCH_FCVT_D_WU 0xd2100053
 #define MASK_FCVT_D_WU  0xfff0007f
 #define MATCH_OR 0x6033
@@ -295,16 +279,10 @@
 #define MASK_AMOMAXU_W  0xf800707f
 #define MATCH_FCVT_WU_S 0xc0100053
 #define MASK_FCVT_WU_S  0xfff0007f
-#define MATCH_CUSTOM3_RD 0x407b
-#define MASK_CUSTOM3_RD  0x707f
-#define MATCH_CUSTOM0_RS1 0x200b
-#define MASK_CUSTOM0_RS1  0x707f
 #define MATCH_ANDI 0x7013
 #define MASK_ANDI  0x707f
 #define MATCH_FMV_X_S 0xe0000053
 #define MASK_FMV_X_S  0xfff0707f
-#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
 #define MATCH_SRET 0x80000073
 #define MASK_SRET  0xffffffff
 #define MATCH_FNMADD_S 0x4f
@@ -315,16 +293,12 @@
 #define MASK_LWU  0x707f
 #define MATCH_FMV_X_D 0xe2000053
 #define MASK_FMV_X_D  0xfff0707f
-#define MATCH_CUSTOM0_RD 0x400b
-#define MASK_CUSTOM0_RD  0x707f
 #define MATCH_FCVT_D_S 0x42000053
 #define MASK_FCVT_D_S  0xfff0007f
 #define MATCH_FNMADD_D 0x200004f
 #define MASK_FNMADD_D  0x600007f
 #define MATCH_AMOADD_D 0x302f
 #define MASK_AMOADD_D  0xf800707f
-#define MATCH_CUSTOM3_RD_RS1 0x607b
-#define MASK_CUSTOM3_RD_RS1  0x707f
 #define MATCH_LR_D 0x1000302f
 #define MASK_LR_D  0xf9f0707f
 #define MATCH_FCVT_W_S 0xc0000053
@@ -337,12 +311,8 @@
 #define MASK_FCVT_D_LU  0xfff0007f
 #define MATCH_LR_W 0x1000202f
 #define MASK_LR_W  0xf9f0707f
-#define MATCH_CUSTOM3_RS1_RS2 0x307b
-#define MASK_CUSTOM3_RS1_RS2  0x707f
 #define MATCH_FCVT_W_D 0xc2000053
 #define MASK_FCVT_W_D  0xfff0007f
-#define MATCH_CUSTOM1_RS1_RS2 0x302b
-#define MASK_CUSTOM1_RS1_RS2  0x707f
 #define MATCH_SLT 0x2033
 #define MASK_SLT  0xfe00707f
 #define MATCH_SLLW 0x103b
@@ -359,12 +329,8 @@
 #define MASK_REMW  0xfe00707f
 #define MATCH_SLTU 0x3033
 #define MASK_SLTU  0xfe00707f
-#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
 #define MATCH_SLLI 0x1013
 #define MASK_SLLI  0xfc00707f
-#define MATCH_CUSTOM2_RD 0x405b
-#define MASK_CUSTOM2_RD  0x707f
 #define MATCH_AMOOR_W 0x4000202f
 #define MASK_AMOOR_W  0xf800707f
 #define MATCH_BEQ 0x63
@@ -379,18 +345,8 @@
 #define MASK_FMV_D_X  0xfff0707f
 #define MATCH_LBU 0x4003
 #define MASK_LBU  0x707f
-#define MATCH_CUSTOM2_RS1_RS2 0x305b
-#define MASK_CUSTOM2_RS1_RS2  0x707f
 #define MATCH_FSGNJ_S 0x20000053
 #define MASK_FSGNJ_S  0xfe00707f
-#define MATCH_CUSTOM0 0xb
-#define MASK_CUSTOM0  0x707f
-#define MATCH_CUSTOM1 0x2b
-#define MASK_CUSTOM1  0x707f
-#define MATCH_CUSTOM2 0x5b
-#define MASK_CUSTOM2  0x707f
-#define MATCH_CUSTOM3 0x7b
-#define MASK_CUSTOM3  0x707f
 #define MATCH_AMOMAX_W 0xa000202f
 #define MASK_AMOMAX_W  0xf800707f
 #define MATCH_FSGNJ_D 0x22000053
@@ -405,8 +361,6 @@
 #define MASK_FCVT_LU_S  0xfff0007f
 #define MATCH_FCVT_S_L 0xd0200053
 #define MASK_FCVT_S_L  0xfff0007f
-#define MATCH_CUSTOM0_RD_RS1 0x600b
-#define MASK_CUSTOM0_RD_RS1  0x707f
 #define MATCH_AUIPC 0x17
 #define MASK_AUIPC  0x7f
 #define MATCH_FCVT_LU_D 0xc2300053
@@ -441,8 +395,6 @@
 #define MASK_JALR  0x707f
 #define MATCH_FSD 0x3027
 #define MASK_FSD  0x707f
-#define MATCH_CUSTOM2_RS1 0x205b
-#define MASK_CUSTOM2_RS1  0x707f
 #define MATCH_SW 0x2023
 #define MASK_SW  0x707f
 #define MATCH_FMSUB_S 0x47
@@ -520,7 +472,6 @@
 #endif
 #ifdef DECLARE_INSN
 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
-DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
@@ -528,11 +479,9 @@ DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
@@ -559,7 +508,6 @@ DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
 DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
@@ -574,7 +522,6 @@ DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
@@ -602,12 +549,9 @@ DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
 DECLARE_INSN(or, MATCH_OR, MASK_OR)
 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
@@ -618,30 +562,23 @@ DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
-DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
@@ -650,9 +587,7 @@ DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
@@ -660,12 +595,7 @@ DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
 DECLARE_INSN(and, MATCH_AND, MASK_AND)
 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
@@ -673,7 +603,6 @@ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
@@ -691,7 +620,6 @@ DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)