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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-25 15:32:40 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-25 15:32:40 -0800 |
| commit | 410fb0384f0fac770ab89b675939790d9253bbf1 (patch) | |
| tree | 9fa308c55007e01bef77ebe12ae7f3d8e387f4dc /machine/minit.c | |
| parent | 34979b93458d685df65a49bca3084eb8283439da (diff) | |
| download | pk-410fb0384f0fac770ab89b675939790d9253bbf1.zip pk-410fb0384f0fac770ab89b675939790d9253bbf1.tar.gz pk-410fb0384f0fac770ab89b675939790d9253bbf1.tar.bz2 | |
New counter-enable scheme
https://github.com/riscv/riscv-isa-manual/issues/10
Diffstat (limited to 'machine/minit.c')
| -rw-r--r-- | machine/minit.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/machine/minit.c b/machine/minit.c index 0a1e37e..9a3b01c 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -18,9 +18,11 @@ static void mstatus_init() write_csr(mstatus, MSTATUS_FS); // Enable user/supervisor use of perf counters - write_csr(mucounteren, -1); - write_csr(mscounteren, -1); - write_csr(mie, ~MIP_MTIP); // disable timer; enable other interrupts + write_csr(scounteren, -1); + write_csr(mcounteren, -1); + + // Enable software interrupts + write_csr(mie, MIP_MSIP); // Disable paging write_csr(sptbr, 0); |