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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-04-30 17:39:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-04-30 17:44:09 -0700 |
| commit | 7389e46cd013e0cd23af8a6531e9e104b5a31d09 (patch) | |
| tree | 65a2567c46be9fa73f958cf1863f03925d335cda /machine/mentry.S | |
| parent | 1a9aefdd006b660093283b039bfa8931319f8ae3 (diff) | |
| download | pk-7389e46cd013e0cd23af8a6531e9e104b5a31d09.zip pk-7389e46cd013e0cd23af8a6531e9e104b5a31d09.tar.gz pk-7389e46cd013e0cd23af8a6531e9e104b5a31d09.tar.bz2 | |
Move DRAM to high addresses
Diffstat (limited to 'machine/mentry.S')
| -rw-r--r-- | machine/mentry.S | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/machine/mentry.S b/machine/mentry.S index 49f163b..bbc1c2a 100644 --- a/machine/mentry.S +++ b/machine/mentry.S @@ -89,7 +89,7 @@ trap_vector: STORE t2, 7*REGBYTES(sp) add t1, t0, t1 # t1 <- %hi(trap_table)[mcause] STORE s0, 8*REGBYTES(sp) - lw t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause] + LWU t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause] STORE s1, 9*REGBYTES(sp) mv a0, sp # a0 <- regs STORE a2,12*REGBYTES(sp) @@ -223,6 +223,12 @@ do_reset: li x31, 0 csrw mscratch, x0 + # write mtvec and make sure it sticks + la t0, trap_vector + csrw mtvec, t0 + csrr t1, mtvec +1:bne t0, t1, 1b + # sp <- end of first full page after the end of the binary la sp, _end + 2*RISCV_PGSIZE - 1 li t0, -RISCV_PGSIZE |