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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-10-25 17:10:21 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-10-25 17:10:21 -0700 |
| commit | 6c1d0604dcabf36a6a8d8d9a839b2d4634e202d2 (patch) | |
| tree | 1fce6d9110fe4404663463a3457a45f71f384547 /machine/mentry.S | |
| parent | f81b722bf004177eadaf6f1b4b9e699e20257521 (diff) | |
| download | pk-6c1d0604dcabf36a6a8d8d9a839b2d4634e202d2.zip pk-6c1d0604dcabf36a6a8d8d9a839b2d4634e202d2.tar.gz pk-6c1d0604dcabf36a6a8d8d9a839b2d4634e202d2.tar.bz2 | |
Use __riscv_flen macro to detect FP support
Diffstat (limited to 'machine/mentry.S')
| -rw-r--r-- | machine/mentry.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/machine/mentry.S b/machine/mentry.S index 64c60c3..95653c1 100644 --- a/machine/mentry.S +++ b/machine/mentry.S @@ -107,7 +107,7 @@ trap_vector: STORE t6,31*REGBYTES(sp) STORE t0, 2*REGBYTES(sp) # sp -#ifndef __riscv_hard_float +#ifndef __riscv_flen lw tp, (sp) # Move the emulated FCSR from x0's save slot into tp. #endif STORE x0, (sp) # Zero x0's save slot. @@ -115,7 +115,7 @@ trap_vector: # Invoke the handler. jalr t1 -#ifndef __riscv_hard_float +#ifndef __riscv_flen sw tp, (sp) # Move the emulated FCSR from tp into x0's save slot. #endif |