diff options
author | Andrew Waterman <andrew@sifive.com> | 2017-02-15 15:26:09 -0800 |
---|---|---|
committer | Andrew Waterman <andrew@sifive.com> | 2017-02-15 15:26:09 -0800 |
commit | 15a111444d6819021328e990eb5308155a9def6a (patch) | |
tree | bd5c666e88f2547ad8ffab903b086b492a0027d8 /machine/emulation.h | |
parent | 4678e84c040531a48eff2108fd9212660bf527ae (diff) | |
download | pk-15a111444d6819021328e990eb5308155a9def6a.zip pk-15a111444d6819021328e990eb5308155a9def6a.tar.gz pk-15a111444d6819021328e990eb5308155a9def6a.tar.bz2 |
Emulate RVFC instructions
Diffstat (limited to 'machine/emulation.h')
-rw-r--r-- | machine/emulation.h | 37 |
1 files changed, 30 insertions, 7 deletions
diff --git a/machine/emulation.h b/machine/emulation.h index b8712b5..156d847 100644 --- a/machine/emulation.h +++ b/machine/emulation.h @@ -5,22 +5,45 @@ #include "bits.h" #include <stdint.h> -typedef uint32_t insn_t; +typedef uintptr_t insn_t; typedef void (*emulation_func)(uintptr_t*, uintptr_t, uintptr_t, uintptr_t, insn_t); #define DECLARE_EMULATION_FUNC(name) void name(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc, uintptr_t mstatus, insn_t insn) void misaligned_load_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc); void misaligned_store_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc); -void redirect_trap(uintptr_t epc, uintptr_t mstatus) __attribute__((noreturn)); -DECLARE_EMULATION_FUNC(truly_illegal_insn) __attribute__((noreturn)); +void redirect_trap(uintptr_t epc, uintptr_t mstatus); +DECLARE_EMULATION_FUNC(truly_illegal_insn); +DECLARE_EMULATION_FUNC(emulate_rvc_0); +DECLARE_EMULATION_FUNC(emulate_rvc_2); +#define SH_RD 7 +#define SH_RS1 15 +#define SH_RS2 20 +#define SH_RS2C 2 + +#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) +#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) +#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) +#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) +#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) +#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) +#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) +#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) +#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) +#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) + +#define SHIFT_RIGHT(x, y) ((y) < 0 ? ((x) << -(y)) : ((x) >> (y))) #define GET_REG(insn, pos, regs) ({ \ int mask = (1 << (5+LOG_REGBYTES)) - (1 << LOG_REGBYTES); \ - (uintptr_t*)((uintptr_t)regs + (((insn) >> ((pos) - LOG_REGBYTES)) & mask)); \ + (uintptr_t*)((uintptr_t)regs + (SHIFT_RIGHT(insn, (pos) - LOG_REGBYTES) & (mask))); \ }) -#define GET_RS1(insn, regs) (*GET_REG(insn, 15, regs)) -#define GET_RS2(insn, regs) (*GET_REG(insn, 20, regs)) -#define SET_RD(insn, regs, val) (*GET_REG(insn, 7, regs) = (val)) +#define GET_RS1(insn, regs) (*GET_REG(insn, SH_RS1, regs)) +#define GET_RS2(insn, regs) (*GET_REG(insn, SH_RS2, regs)) +#define GET_RS1S(insn, regs) (*GET_REG(RVC_RS1S(insn), 0, regs)) +#define GET_RS2S(insn, regs) (*GET_REG(RVC_RS2S(insn), 0, regs)) +#define GET_RS2C(insn, regs) (*GET_REG(insn, SH_RS2C, regs)) +#define GET_SP(regs) (*GET_REG(2, 0, regs)) +#define SET_RD(insn, regs, val) (*GET_REG(insn, SH_RD, regs) = (val)) #define IMM_I(insn) ((int32_t)(insn) >> 20) #define IMM_S(insn) (((int32_t)(insn) >> 25 << 5) | (int32_t)(((insn) >> 7) & 0x1f)) #define MASK_FUNCT3 0x7000 |