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authorZong Li <zong@andestech.com>2018-05-09 11:30:19 +0800
committerZong Li <zong@andestech.com>2018-05-09 11:30:31 +0800
commit9ecbd23d6205a7e18ba17a847d49d32993c97421 (patch)
tree41d25ead2c65b349d01efc7612edc5d238a0cab4
parent9d0911092df8e9bd483edf495a9a780e5f0e660f (diff)
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Correct the comment of timer interrupt
-rw-r--r--machine/mentry.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/machine/mentry.S b/machine/mentry.S
index 6746f98..ede40bb 100644
--- a/machine/mentry.S
+++ b/machine/mentry.S
@@ -48,7 +48,7 @@ trap_vector:
li a0, IRQ_M_TIMER * 2
bne a0, a1, 1f
- # Yes. Simply clear MSIE and raise SSIP.
+ # Yes. Simply clear MTIE and raise STIP.
li a0, MIP_MTIP
csrc mie, a0
li a0, MIP_STIP