[xcc,opcodes,pk,sim] krste's re-renaming spree

4 files changed, 193 insertions, 199 deletions

diff --git a/pk/entry.S b/pk/entry.S
index 57acc69..d2fb72c 100644
--- a/pk/entry.S
+++ b/pk/entry.S
@@ -1,12 +1,12 @@
 #include "pcr.h"
 
 #ifdef PK_ENABLE_KERNEL_64BIT
-# define STORE    s.d
-# define LOAD     l.d
+# define STORE    sd
+# define LOAD     ld
 # define REGBYTES 8
 #else
-# define STORE    s.w
-# define LOAD     l.w
+# define STORE    sw
+# define LOAD     lw
 # define REGBYTES 4
 #endif
 
@@ -62,7 +62,7 @@ save_tf:	# write the trap frame onto the stack
 
 	# get insn
 	and		$x4,$x4,~3
-	l.w		$x3,0($x4)
+	lw		$x3,0($x4)
 	STORE	$x3, 36*REGBYTES($x2)
 
 	ret
diff --git a/pk/fp.c b/pk/fp.c
index 587cc3f..25b0393 100644
--- a/pk/fp.c
+++ b/pk/fp.c
@@ -65,63 +65,57 @@ int emulate_fp(trapframe_t* tf)
 
   #define IS_INSN(x) ((tf->insn & MASK_ ## x) == MATCH_ ## x)
 
-  if(IS_INSN(LF_W))
+  if(IS_INSN(FLW))
   {
     validate_address(tf, effective_address_load, 4, 0);
     set_fp_reg(RRD, 0, *(uint32_t*)effective_address_load);
   }
-  else if(IS_INSN(LF_D))
+  else if(IS_INSN(FLD))
   {
     validate_address(tf, effective_address_load, 8, 0);
     set_fp_reg(RRD, 1, *(uint64_t*)effective_address_load);
   }
-  else if(IS_INSN(SF_W))
+  else if(IS_INSN(FSW))
   {
     validate_address(tf, effective_address_store, 4, 1);
     *(uint32_t*)effective_address_store = frs2s;
   }
-  else if(IS_INSN(SF_D))
+  else if(IS_INSN(FSD))
   {
     validate_address(tf, effective_address_store, 8, 1);
     *(uint64_t*)effective_address_store = frs2d;
   }
-  else if(IS_INSN(MFF_S))
+  else if(IS_INSN(MFTX_S))
     XRDR = frs2s;
-  else if(IS_INSN(MFF_D))
+  else if(IS_INSN(MFTX_D))
     XRDR = frs2d;
-  else if(IS_INSN(MFFL_D))
-    XRDR = (int32_t)frs2d;
-  else if(IS_INSN(MFFH_D))
-    XRDR = (int64_t)frs2d >> 32;
-  else if(IS_INSN(MTF_S))
+  else if(IS_INSN(MXTF_S))
     set_fp_reg(RRD, 0, XRS1);
-  else if(IS_INSN(MTF_D))
+  else if(IS_INSN(MXTF_D))
     set_fp_reg(RRD, 1, XRS1);
-  else if(IS_INSN(MTFLH_D))
-    set_fp_reg(RRD, 1, (uint32_t)XRS1 | (XRS2 << 32));
-  else if(IS_INSN(FSINJ_S))
+  else if(IS_INSN(FSGNJ_S))
     set_fp_reg(RRD, 0, (frs1s &~ (uint32_t)INT32_MIN) | (frs2s & (uint32_t)INT32_MIN));
-  else if(IS_INSN(FSINJ_D))
+  else if(IS_INSN(FSGNJ_D))
     set_fp_reg(RRD, 1, (frs1d &~ INT64_MIN) | (frs2d & INT64_MIN));
-  else if(IS_INSN(FSINJN_S))
+  else if(IS_INSN(FSGNJN_S))
     set_fp_reg(RRD, 0, (frs1s &~ (uint32_t)INT32_MIN) | ((~frs2s) & (uint32_t)INT32_MIN));
-  else if(IS_INSN(FSINJN_D))
+  else if(IS_INSN(FSGNJN_D))
     set_fp_reg(RRD, 1, (frs1d &~ INT64_MIN) | ((~frs2d) & INT64_MIN));
-  else if(IS_INSN(FSMUL_S))
+  else if(IS_INSN(FSGNJX_S))
     set_fp_reg(RRD, 0, frs1s ^ (frs2s & (uint32_t)INT32_MIN));
-  else if(IS_INSN(FSMUL_D))
+  else if(IS_INSN(FSGNJX_D))
     set_fp_reg(RRD, 1, frs1d ^ (frs2d & INT64_MIN));
-  else if(IS_INSN(FC_EQ_S))
+  else if(IS_INSN(FEQ_S))
     XRDR = f32_eq(frs1s, frs2s);
-  else if(IS_INSN(FC_EQ_D))
+  else if(IS_INSN(FEQ_D))
     XRDR = f64_eq(frs1d, frs2d);
-  else if(IS_INSN(FC_LE_S))
+  else if(IS_INSN(FLE_S))
     XRDR = f32_le(frs1s, frs2s);
-  else if(IS_INSN(FC_LE_D))
+  else if(IS_INSN(FLE_D))
     XRDR = f64_le(frs1d, frs2d);
-  else if(IS_INSN(FC_LT_S))
+  else if(IS_INSN(FLT_S))
     XRDR = f32_lt(frs1s, frs2s);
-  else if(IS_INSN(FC_LT_D))
+  else if(IS_INSN(FLT_D))
     XRDR = f64_lt(frs1d, frs2d);
   else if(IS_INSN(FCVT_S_W))
     set_fp_reg(RRD, 0, i32_to_f32(XRS1));
@@ -135,13 +129,13 @@ int emulate_fp(trapframe_t* tf)
     set_fp_reg(RRD, 1, i64_to_f64(XRS1));
   else if(IS_INSN(FCVT_D_S))
     set_fp_reg(RRD, 1, f32_to_f64(frs1s));
-  else if(IS_INSN(FCVTU_S_W))
+  else if(IS_INSN(FCVT_S_WU))
     set_fp_reg(RRD, 0, ui32_to_f32(XRS1));
-  else if(IS_INSN(FCVTU_S_L))
+  else if(IS_INSN(FCVT_S_LU))
     set_fp_reg(RRD, 0, ui64_to_f32(XRS1));
-  else if(IS_INSN(FCVTU_D_W))
+  else if(IS_INSN(FCVT_D_WU))
     set_fp_reg(RRD, 1, ui32_to_f64(XRS1));
-  else if(IS_INSN(FCVTU_D_L))
+  else if(IS_INSN(FCVT_D_LU))
     set_fp_reg(RRD, 1, ui64_to_f64(XRS1));
   else if(IS_INSN(FADD_S))
     set_fp_reg(RRD, 0, f32_add(frs1s, frs2s));
@@ -187,13 +181,13 @@ int emulate_fp(trapframe_t* tf)
     XRDR = f32_to_i64_r_minMag(frs1s,true);
   else if(IS_INSN(FCVT_L_D))
     XRDR = f64_to_i64_r_minMag(frs1d,true);
-  else if(IS_INSN(FCVTU_W_S))
+  else if(IS_INSN(FCVT_WU_S))
     XRDR = f32_to_ui32_r_minMag(frs1s,true);
-  else if(IS_INSN(FCVTU_W_D))
+  else if(IS_INSN(FCVT_WU_D))
     XRDR = f64_to_ui32_r_minMag(frs1d,true);
-  else if(IS_INSN(FCVTU_L_S))
+  else if(IS_INSN(FCVT_LU_S))
     XRDR = f32_to_ui64_r_minMag(frs1s,true);
-  else if(IS_INSN(FCVTU_L_D))
+  else if(IS_INSN(FCVT_LU_D))
     XRDR = f64_to_ui64_r_minMag(frs1d,true);
   else
     return -1;
@@ -209,10 +203,10 @@ int emulate_fp(trapframe_t* tf)
 #define STR(x) XSTR(x)
 #define XSTR(x) #x
 
-#define PUT_FP_REG(which, type, val) asm("mtf." STR(type) " $f" STR(which) ",%0" : : "r"(val))
-#define GET_FP_REG(which, type, val) asm("mff." STR(type) " %0,$f" STR(which) : "=r"(val))
-#define LOAD_FP_REG(which, type, val) asm("l." STR(type) " $f" STR(which) ",%0" : : "m"(val))
-#define STORE_FP_REG(which, type, val)  asm("s." STR(type) " $f" STR(which) ",%0" : "=m"(val) : : "memory")
+#define PUT_FP_REG(which, type, val) asm("mxtf." STR(type) " $f" STR(which) ",%0" : : "r"(val))
+#define GET_FP_REG(which, type, val) asm("mftx." STR(type) " %0,$f" STR(which) : "=r"(val))
+#define LOAD_FP_REG(which, type, val) asm("fl" STR(type) " $f" STR(which) ",%0" : : "m"(val))
+#define STORE_FP_REG(which, type, val)  asm("fs" STR(type) " $f" STR(which) ",%0" : "=m"(val) : : "memory")
 
 static void __attribute__((noinline))
 set_fp_reg(unsigned int which, unsigned int dp, uint64_t val)
@@ -231,7 +225,7 @@ set_fp_reg(unsigned int which, unsigned int dp, uint64_t val)
     // then move it back out as a DP value.  OK to clobber $f0
     // because we'll restore it later.
     PUT_FP_REG(0,s,val);
-    GET_FP_REG(0,d,fp_state.fpr[which]);
+    STORE_FP_REG(0,d,fp_state.fpr[which]);
   }
 }
 
@@ -246,7 +240,7 @@ get_fp_reg(unsigned int which, unsigned int dp)
     // to get an SP value, move the DP value into the FPU
     // then move it back out as an SP value.  OK to clobber $f0
     // because we'll restore it later.
-    PUT_FP_REG(0,d,fp_state.fpr[which]);
+    LOAD_FP_REG(0,d,fp_state.fpr[which]);
     GET_FP_REG(0,s,val);
   }
 
diff --git a/pk/fp_asm.S b/pk/fp_asm.S
index 67589a8..c6c8bba 100644
--- a/pk/fp_asm.S
+++ b/pk/fp_asm.S
@@ -7,38 +7,38 @@ get_fp_state:
 
 	mffsr	$v0
 
-	sf.d		$f0 ,  0($a0)
-	sf.d		$f1 ,  8($a0)
-	sf.d		$f2 , 16($a0)
-	sf.d		$f3 , 24($a0)
-	sf.d		$f4 , 32($a0)
-	sf.d		$f5 , 40($a0)
-	sf.d		$f6 , 48($a0)
-	sf.d		$f7 , 56($a0)
-	sf.d		$f8 , 64($a0)
-	sf.d		$f9 , 72($a0)
-	sf.d		$f10, 80($a0)
-	sf.d		$f11, 88($a0)
-	sf.d		$f12, 96($a0)
-	sf.d		$f13,104($a0)
-	sf.d		$f14,112($a0)
-	sf.d		$f15,120($a0)
-	sf.d		$f16,128($a0)
-	sf.d		$f17,136($a0)
-	sf.d		$f18,144($a0)
-	sf.d		$f19,152($a0)
-	sf.d		$f20,160($a0)
-	sf.d		$f21,168($a0)
-	sf.d		$f22,176($a0)
-	sf.d		$f23,184($a0)
-	sf.d		$f24,192($a0)
-	sf.d		$f25,200($a0)
-	sf.d		$f26,208($a0)
-	sf.d		$f27,216($a0)
-	sf.d		$f28,224($a0)
-	sf.d		$f29,232($a0)
-	sf.d		$f30,240($a0)
-	sf.d		$f31,248($a0)
+	fsd		$f0 ,  0($a0)
+	fsd		$f1 ,  8($a0)
+	fsd		$f2 , 16($a0)
+	fsd		$f3 , 24($a0)
+	fsd		$f4 , 32($a0)
+	fsd		$f5 , 40($a0)
+	fsd		$f6 , 48($a0)
+	fsd		$f7 , 56($a0)
+	fsd		$f8 , 64($a0)
+	fsd		$f9 , 72($a0)
+	fsd		$f10, 80($a0)
+	fsd		$f11, 88($a0)
+	fsd		$f12, 96($a0)
+	fsd		$f13,104($a0)
+	fsd		$f14,112($a0)
+	fsd		$f15,120($a0)
+	fsd		$f16,128($a0)
+	fsd		$f17,136($a0)
+	fsd		$f18,144($a0)
+	fsd		$f19,152($a0)
+	fsd		$f20,160($a0)
+	fsd		$f21,168($a0)
+	fsd		$f22,176($a0)
+	fsd		$f23,184($a0)
+	fsd		$f24,192($a0)
+	fsd		$f25,200($a0)
+	fsd		$f26,208($a0)
+	fsd		$f27,216($a0)
+	fsd		$f28,224($a0)
+	fsd		$f29,232($a0)
+	fsd		$f30,240($a0)
+	fsd		$f31,248($a0)
 
 	ret
 
@@ -48,38 +48,38 @@ get_fp_state:
 	.ent	put_fp_state
 put_fp_state:
 
-	lf.d		$f0 ,  0($a0)
-	lf.d		$f1 ,  8($a0)
-	lf.d		$f2 , 16($a0)
-	lf.d		$f3 , 24($a0)
-	lf.d		$f4 , 32($a0)
-	lf.d		$f5 , 40($a0)
-	lf.d		$f6 , 48($a0)
-	lf.d		$f7 , 56($a0)
-	lf.d		$f8 , 64($a0)
-	lf.d		$f9 , 72($a0)
-	lf.d		$f10, 80($a0)
-	lf.d		$f11, 88($a0)
-	lf.d		$f12, 96($a0)
-	lf.d		$f13,104($a0)
-	lf.d		$f14,112($a0)
-	lf.d		$f15,120($a0)
-	lf.d		$f16,128($a0)
-	lf.d		$f17,136($a0)
-	lf.d		$f18,144($a0)
-	lf.d		$f19,152($a0)
-	lf.d		$f20,160($a0)
-	lf.d		$f21,168($a0)
-	lf.d		$f22,176($a0)
-	lf.d		$f23,184($a0)
-	lf.d		$f24,192($a0)
-	lf.d		$f25,200($a0)
-	lf.d		$f26,208($a0)
-	lf.d		$f27,216($a0)
-	lf.d		$f28,224($a0)
-	lf.d		$f29,232($a0)
-	lf.d		$f30,240($a0)
-	lf.d		$f31,248($a0)
+	fld		$f0 ,  0($a0)
+	fld		$f1 ,  8($a0)
+	fld		$f2 , 16($a0)
+	fld		$f3 , 24($a0)
+	fld		$f4 , 32($a0)
+	fld		$f5 , 40($a0)
+	fld		$f6 , 48($a0)
+	fld		$f7 , 56($a0)
+	fld		$f8 , 64($a0)
+	fld		$f9 , 72($a0)
+	fld		$f10, 80($a0)
+	fld		$f11, 88($a0)
+	fld		$f12, 96($a0)
+	fld		$f13,104($a0)
+	fld		$f14,112($a0)
+	fld		$f15,120($a0)
+	fld		$f16,128($a0)
+	fld		$f17,136($a0)
+	fld		$f18,144($a0)
+	fld		$f19,152($a0)
+	fld		$f20,160($a0)
+	fld		$f21,168($a0)
+	fld		$f22,176($a0)
+	fld		$f23,184($a0)
+	fld		$f24,192($a0)
+	fld		$f25,200($a0)
+	fld		$f26,208($a0)
+	fld		$f27,216($a0)
+	fld		$f28,224($a0)
+	fld		$f29,232($a0)
+	fld		$f30,240($a0)
+	fld		$f31,248($a0)
 
 	mtfsr	$a1
 
diff --git a/pk/riscv-opc.h b/pk/riscv-opc.h
index 21b7d0f..8ec112d 100644
--- a/pk/riscv-opc.h
+++ b/pk/riscv-opc.h
@@ -1,30 +1,28 @@
 /* Automatically generated by parse-opcodes */
-#define MATCH_MFF_D 0x18ed3
-#define  MASK_MFF_D 0x7c1ffff
-#define MATCH_FSINJN_D 0x6ed3
-#define  MASK_FSINJN_D 0x1ffff
 #define MATCH_REMUW 0x7bb
 #define  MASK_REMUW 0x1ffff
 #define MATCH_BLTU 0x363
 #define  MASK_BLTU 0x3ff
-#define MATCH_FSINJN_S 0x6e53
-#define  MASK_FSINJN_S 0x1ffff
-#define MATCH_MFF_S 0x18e53
-#define  MASK_MFF_S 0x7c1ffff
+#define MATCH_FCVT_LU_S 0x9053
+#define  MASK_FCVT_LU_S 0x3ff1ff
 #define MATCH_MTFSR 0x1de53
 #define  MASK_MTFSR 0xf83fffff
 #define MATCH_SLLIW 0x9b
 #define  MASK_SLLIW 0x3f83ff
+#define MATCH_LB 0x3
+#define  MASK_LB 0x3ff
 #define MATCH_FCVT_D_L 0xc0d3
 #define  MASK_FCVT_D_L 0x3ff1ff
+#define MATCH_LH 0x83
+#define  MASK_LH 0x3ff
 #define MATCH_FCVT_D_W 0xeed3
 #define  MASK_FCVT_D_W 0x3fffff
+#define MATCH_LW 0x103
+#define  MASK_LW 0x3ff
 #define MATCH_ADD 0x33
 #define  MASK_ADD 0x1ffff
-#define MATCH_FCVT_D_S 0x10ed3
-#define  MASK_FCVT_D_S 0x3fffff
-#define MATCH_LF_D 0x187
-#define  MASK_LF_D 0x3ff
+#define MATCH_FCVT_D_S 0x100d3
+#define  MASK_FCVT_D_S 0x3ff1ff
 #define MATCH_MFPCR 0xff
 #define  MASK_MFPCR 0x7c1ffff
 #define MATCH_BNE 0xe3
@@ -47,44 +45,40 @@
 #define  MASK_MUL 0x1ffff
 #define MATCH_AMOMINU_D 0x19c3
 #define  MASK_AMOMINU_D 0x1ffff
+#define MATCH_MFTX_D 0x18ed3
+#define  MASK_MFTX_D 0x7c1ffff
 #define MATCH_SRLI 0x293
 #define  MASK_SRLI 0x3f03ff
-#define MATCH_FCVTU_W_S 0xb053
-#define  MASK_FCVTU_W_S 0x3ff1ff
 #define MATCH_AMOMINU_W 0x1943
 #define  MASK_AMOMINU_W 0x1ffff
 #define MATCH_DIVUW 0x6bb
 #define  MASK_DIVUW 0x1ffff
+#define MATCH_MULW 0x43b
+#define  MASK_MULW 0x1ffff
 #define MATCH_SRLW 0x2bb
 #define  MASK_SRLW 0x1ffff
 #define MATCH_DIV 0x633
 #define  MASK_DIV 0x1ffff
-#define MATCH_S_D 0x1a3
-#define  MASK_S_D 0x3ff
+#define MATCH_MFTX_S 0x18e53
+#define  MASK_MFTX_S 0x7c1ffff
 #define MATCH_J 0x67
 #define  MASK_J 0x7f
-#define MATCH_S_B 0x23
-#define  MASK_S_B 0x3ff
+#define MATCH_EI 0x7f
+#define  MASK_EI 0x7ffffff
 #define MATCH_FNMSUB_S 0x4b
 #define  MASK_FNMSUB_S 0x1ff
 #define MATCH_FCVT_L_S 0x8053
 #define  MASK_FCVT_L_S 0x3ff1ff
 #define MATCH_SYNC 0x117
 #define  MASK_SYNC 0xffffffff
-#define MATCH_S_H 0xa3
-#define  MASK_S_H 0x3ff
-#define MATCH_MTF_S 0x1ce53
-#define  MASK_MTF_S 0x3fffff
-#define MATCH_S_W 0x123
-#define  MASK_S_W 0x3ff
+#define MATCH_FLE_S 0x17e53
+#define  MASK_FLE_S 0x1ffff
 #define MATCH_MFFSR 0x1be53
 #define  MASK_MFFSR 0x7ffffff
 #define MATCH_FDIV_S 0x3053
 #define  MASK_FDIV_S 0x1f1ff
-#define MATCH_SF_D 0x1a7
-#define  MASK_SF_D 0x3ff
-#define MATCH_MTF_D 0x1ced3
-#define  MASK_MTF_D 0x3fffff
+#define MATCH_FLE_D 0x17ed3
+#define  MASK_FLE_D 0x1ffff
 #define MATCH_FCVT_L_D 0x80d3
 #define  MASK_FCVT_L_D 0x3ff1ff
 #define MATCH_FNMSUB_D 0xcb
@@ -99,24 +93,18 @@
 #define  MASK_SUB 0x1ffff
 #define MATCH_ERET 0x17f
 #define  MASK_ERET 0xffffffff
-#define MATCH_FCVTU_D_W 0xfed3
-#define  MASK_FCVTU_D_W 0x3fffff
 #define MATCH_BLT 0x263
 #define  MASK_BLT 0x3ff
-#define MATCH_FC_LT_S 0x16e53
-#define  MASK_FC_LT_S 0x1ffff
 #define MATCH_REM 0x733
 #define  MASK_REM 0x1ffff
 #define MATCH_SRLIW 0x29b
 #define  MASK_SRLIW 0x3f83ff
 #define MATCH_LUI 0x37
 #define  MASK_LUI 0x7f
-#define MATCH_L_W 0x103
-#define  MASK_L_W 0x3ff
+#define MATCH_FCVT_S_LU 0xd053
+#define  MASK_FCVT_S_LU 0x3ff1ff
 #define MATCH_ADDI 0x13
 #define  MASK_ADDI 0x3ff
-#define MATCH_FC_LT_D 0x16ed3
-#define  MASK_FC_LT_D 0x1ffff
 #define MATCH_MULH 0x4b3
 #define  MASK_MULH 0x1ffff
 #define MATCH_FMUL_S 0x2053
@@ -125,40 +113,50 @@
 #define  MASK_SRAI 0x3f03ff
 #define MATCH_AMOAND_D 0x9c3
 #define  MASK_AMOAND_D 0x1ffff
+#define MATCH_FLT_D 0x16ed3
+#define  MASK_FLT_D 0x1ffff
 #define MATCH_SRAW 0x102bb
 #define  MASK_SRAW 0x1ffff
 #define MATCH_FMUL_D 0x20d3
 #define  MASK_FMUL_D 0x1f1ff
+#define MATCH_LD 0x183
+#define  MASK_LD 0x3ff
 #define MATCH_ORI 0x313
 #define  MASK_ORI 0x3ff
+#define MATCH_FLT_S 0x16e53
+#define  MASK_FLT_S 0x1ffff
 #define MATCH_ADDIW 0x1b
 #define  MASK_ADDIW 0x3ff
 #define MATCH_AMOAND_W 0x943
 #define  MASK_AMOAND_W 0x1ffff
+#define MATCH_FEQ_S 0x15e53
+#define  MASK_FEQ_S 0x1ffff
+#define MATCH_FSGNJX_D 0x7ed3
+#define  MASK_FSGNJX_D 0x1ffff
 #define MATCH_SRA 0x102b3
 #define  MASK_SRA 0x1ffff
-#define MATCH_L_BU 0x203
-#define  MASK_L_BU 0x3ff
+#define MATCH_BGE 0x2e3
+#define  MASK_BGE 0x3ff
 #define MATCH_SRAIW 0x1029b
 #define  MASK_SRAIW 0x3f83ff
 #define MATCH_SRL 0x2b3
 #define  MASK_SRL 0x1ffff
-#define MATCH_FC_EQ_D 0x15ed3
-#define  MASK_FC_EQ_D 0x1ffff
+#define MATCH_FSGNJX_S 0x7e53
+#define  MASK_FSGNJX_S 0x1ffff
+#define MATCH_FEQ_D 0x15ed3
+#define  MASK_FEQ_D 0x1ffff
+#define MATCH_FCVT_D_WU 0xfed3
+#define  MASK_FCVT_D_WU 0x3fffff
 #define MATCH_OR 0x333
 #define  MASK_OR 0x1ffff
-#define MATCH_FMADD_D 0xc3
-#define  MASK_FMADD_D 0x1ff
+#define MATCH_FCVT_WU_D 0xb0d3
+#define  MASK_FCVT_WU_D 0x3ff1ff
 #define MATCH_SUBW 0x1003b
 #define  MASK_SUBW 0x1ffff
 #define MATCH_JALR_C 0x6b
 #define  MASK_JALR_C 0x3ff
-#define MATCH_LF_W 0x107
-#define  MASK_LF_W 0x3ff
 #define MATCH_AMOMAXU_D 0x1dc3
 #define  MASK_AMOMAXU_D 0x1ffff
-#define MATCH_SF_W 0x127
-#define  MASK_SF_W 0x3ff
 #define MATCH_JALR_J 0x16b
 #define  MASK_JALR_J 0x3ff
 #define MATCH_XORI 0x213
@@ -167,28 +165,22 @@
 #define  MASK_JALR_R 0x3ff
 #define MATCH_AMOMAXU_W 0x1d43
 #define  MASK_AMOMAXU_W 0x1ffff
-#define MATCH_AMOMIN_D 0x11c3
-#define  MASK_AMOMIN_D 0x1ffff
-#define MATCH_EI 0x7f
-#define  MASK_EI 0x7ffffff
-#define MATCH_FSMUL_S 0x7e53
-#define  MASK_FSMUL_S 0x1ffff
+#define MATCH_FCVT_WU_S 0xb053
+#define  MASK_FCVT_WU_S 0x3ff1ff
 #define MATCH_ANDI 0x393
 #define  MASK_ANDI 0x3ff
+#define MATCH_FSGNJN_D 0x6ed3
+#define  MASK_FSGNJN_D 0x1ffff
 #define MATCH_FNMADD_S 0x4f
 #define  MASK_FNMADD_S 0x1ff
 #define MATCH_JAL 0x6f
 #define  MASK_JAL 0x7f
-#define MATCH_MULW 0x43b
-#define  MASK_MULW 0x1ffff
-#define MATCH_FSMUL_D 0x7ed3
-#define  MASK_FSMUL_D 0x1ffff
+#define MATCH_LWU 0x303
+#define  MASK_LWU 0x3ff
 #define MATCH_FNMADD_D 0xcf
 #define  MASK_FNMADD_D 0x1ff
 #define MATCH_AMOADD_D 0x1c3
 #define  MASK_AMOADD_D 0x1ffff
-#define MATCH_FSINJ_D 0x5ed3
-#define  MASK_FSINJ_D 0x1ffff
 #define MATCH_AMOMAX_W 0x1543
 #define  MASK_AMOMAX_W 0x1ffff
 #define MATCH_FCVT_W_S 0xa053
@@ -197,16 +189,16 @@
 #define  MASK_MULHSU 0x1ffff
 #define MATCH_AMOADD_W 0x143
 #define  MASK_AMOADD_W 0x1ffff
-#define MATCH_FSINJ_S 0x5e53
-#define  MASK_FSINJ_S 0x1ffff
+#define MATCH_FCVT_D_LU 0xd0d3
+#define  MASK_FCVT_D_LU 0x3ff1ff
 #define MATCH_AMOMAX_D 0x15c3
 #define  MASK_AMOMAX_D 0x1ffff
 #define MATCH_FCVT_W_D 0xa0d3
 #define  MASK_FCVT_W_D 0x3ff1ff
-#define MATCH_BGE 0x2e3
-#define  MASK_BGE 0x3ff
 #define MATCH_SLT 0x133
 #define  MASK_SLT 0x1ffff
+#define MATCH_MXTF_D 0x1ced3
+#define  MASK_MXTF_D 0x3fffff
 #define MATCH_SLLW 0xbb
 #define  MASK_SLLW 0x1ffff
 #define MATCH_AMOOR_D 0xdc3
@@ -215,50 +207,50 @@
 #define  MASK_SLTI 0x3ff
 #define MATCH_REMU 0x7b3
 #define  MASK_REMU 0x1ffff
+#define MATCH_FLW 0x107
+#define  MASK_FLW 0x3ff
 #define MATCH_REMW 0x73b
 #define  MASK_REMW 0x1ffff
 #define MATCH_SLTU 0x1b3
 #define  MASK_SLTU 0x1ffff
-#define MATCH_L_HU 0x283
-#define  MASK_L_HU 0x3ff
 #define MATCH_SLLI 0x93
 #define  MASK_SLLI 0x3f03ff
 #define MATCH_AMOOR_W 0xd43
 #define  MASK_AMOOR_W 0x1ffff
 #define MATCH_BEQ 0x63
 #define  MASK_BEQ 0x3ff
+#define MATCH_FLD 0x187
+#define  MASK_FLD 0x3ff
+#define MATCH_MXTF_S 0x1ce53
+#define  MASK_MXTF_S 0x3fffff
 #define MATCH_FSUB_S 0x1053
 #define  MASK_FSUB_S 0x1f1ff
 #define MATCH_AND 0x3b3
 #define  MASK_AND 0x1ffff
-#define MATCH_FC_LE_S 0x17e53
-#define  MASK_FC_LE_S 0x1ffff
+#define MATCH_LBU 0x203
+#define  MASK_LBU 0x3ff
 #define MATCH_SYSCALL 0x197
 #define  MASK_SYSCALL 0xffc003ff
-#define MATCH_FCVTU_S_W 0xf053
-#define  MASK_FCVTU_S_W 0x3ff1ff
-#define MATCH_FC_LE_D 0x17ed3
-#define  MASK_FC_LE_D 0x1ffff
-#define MATCH_FCVTU_S_L 0xd053
-#define  MASK_FCVTU_S_L 0x3ff1ff
+#define MATCH_FSGNJ_S 0x5e53
+#define  MASK_FSGNJ_S 0x1ffff
+#define MATCH_FSGNJ_D 0x5ed3
+#define  MASK_FSGNJ_D 0x1ffff
 #define MATCH_MULHU 0x5b3
 #define  MASK_MULHU 0x1ffff
-#define MATCH_FCVTU_W_D 0xb0d3
-#define  MASK_FCVTU_W_D 0x3ff1ff
-#define MATCH_FCVTU_L_S 0x9053
-#define  MASK_FCVTU_L_S 0x3ff1ff
 #define MATCH_FADD_D 0xd3
 #define  MASK_FADD_D 0x1f1ff
+#define MATCH_FCVT_S_WU 0xf053
+#define  MASK_FCVT_S_WU 0x3ff1ff
 #define MATCH_RDNPC 0x17
 #define  MASK_RDNPC 0x7ffffff
 #define MATCH_FCVT_S_L 0xc053
 #define  MASK_FCVT_S_L 0x3ff1ff
 #define MATCH_SYNCI 0x97
 #define  MASK_SYNCI 0xffffffff
+#define MATCH_FCVT_LU_D 0x90d3
+#define  MASK_FCVT_LU_D 0x3ff1ff
 #define MATCH_UNIMP 0x0
 #define  MASK_UNIMP 0xffffffff
-#define MATCH_FCVTU_L_D 0x90d3
-#define  MASK_FCVTU_L_D 0x3ff1ff
 #define MATCH_FSUB_D 0x10d3
 #define  MASK_FSUB_D 0x1f1ff
 #define MATCH_FMADD_S 0x43
@@ -267,31 +259,39 @@
 #define  MASK_FSQRT_S 0x3ff1ff
 #define MATCH_AMOMIN_W 0x1143
 #define  MASK_AMOMIN_W 0x1ffff
+#define MATCH_FSGNJN_S 0x6e53
+#define  MASK_FSGNJN_S 0x1ffff
 #define MATCH_AMOSWAP_D 0x5c3
 #define  MASK_AMOSWAP_D 0x1ffff
 #define MATCH_FSQRT_D 0x40d3
 #define  MASK_FSQRT_D 0x3ff1ff
-#define MATCH_FC_EQ_S 0x15e53
-#define  MASK_FC_EQ_S 0x1ffff
 #define MATCH_FDIV_D 0x30d3
 #define  MASK_FDIV_D 0x1f1ff
-#define MATCH_L_H 0x83
-#define  MASK_L_H 0x3ff
+#define MATCH_FMADD_D 0xc3
+#define  MASK_FMADD_D 0x1ff
 #define MATCH_DIVW 0x63b
 #define  MASK_DIVW 0x1ffff
-#define MATCH_L_D 0x183
-#define  MASK_L_D 0x3ff
+#define MATCH_AMOMIN_D 0x11c3
+#define  MASK_AMOMIN_D 0x1ffff
 #define MATCH_DIVU 0x6b3
 #define  MASK_DIVU 0x1ffff
 #define MATCH_AMOSWAP_W 0x543
 #define  MASK_AMOSWAP_W 0x1ffff
-#define MATCH_FCVTU_D_L 0xd0d3
-#define  MASK_FCVTU_D_L 0x3ff1ff
-#define MATCH_L_B 0x3
-#define  MASK_L_B 0x3ff
-#define MATCH_L_WU 0x303
-#define  MASK_L_WU 0x3ff
+#define MATCH_FSD 0x1a7
+#define  MASK_FSD 0x3ff
+#define MATCH_SW 0x123
+#define  MASK_SW 0x3ff
 #define MATCH_FMSUB_S 0x47
 #define  MASK_FMSUB_S 0x1ff
+#define MATCH_LHU 0x283
+#define  MASK_LHU 0x3ff
+#define MATCH_SH 0xa3
+#define  MASK_SH 0x3ff
+#define MATCH_FSW 0x127
+#define  MASK_FSW 0x3ff
+#define MATCH_SB 0x23
+#define  MASK_SB 0x3ff
 #define MATCH_FMSUB_D 0xc7
 #define  MASK_FMSUB_D 0x1ff
+#define MATCH_SD 0x1a3
+#define  MASK_SD 0x3ff