new supervisor mode

6 files changed, 73 insertions, 70 deletions

diff --git a/pk/file.c b/pk/file.c
index cf370b5..fa7e1e1 100644
--- a/pk/file.c
+++ b/pk/file.c
@@ -125,12 +125,6 @@ sysret_t file_pread(file_t* f, char* buf, size_t size, off_t offset)
 
 sysret_t file_write(file_t* f, const char* buf, size_t size)
 {
-  if(f->kfd == 1 || f->kfd == 2)
-  {
-    for(size_t i = 0; i < size; i++)
-      mtpcr(PCR_CONSOLE,buf[i]);
-  }
-
   return frontend_syscall(SYS_write,f->kfd,(long)buf,size,0);
 }
 
diff --git a/pk/handlers.c b/pk/handlers.c
index fee9a51..da2f915 100644
--- a/pk/handlers.c
+++ b/pk/handlers.c
@@ -48,7 +48,7 @@ static void handle_illegal_instruction(trapframe_t* tf)
 
 static void handle_fp_disabled(trapframe_t* tf)
 {
-  irq_enable();
+  setpcr(PCR_SR, SR_ET);
 
   if(have_fp && !(mfpcr(PCR_SR) & SR_EF))
     init_fp(tf);
@@ -106,7 +106,7 @@ static void handle_timer_interrupt(trapframe_t* tf)
 
 static void handle_syscall(trapframe_t* tf)
 {
-  irq_enable();
+  setpcr(PCR_SR, SR_ET);
 
   long n = tf->gpr[2];
   sysret_t ret = syscall(tf->gpr[4], tf->gpr[5], tf->gpr[6], tf->gpr[7], n);
@@ -121,7 +121,7 @@ void handle_trap(trapframe_t* tf)
 {
   typedef void (*trap_handler)(trapframe_t*);
 
-  const static trap_handler trap_handlers[NUM_CAUSES] = {
+  const static trap_handler trap_handlers[] = {
     [CAUSE_MISALIGNED_FETCH] = handle_misaligned_fetch,
     [CAUSE_FAULT_FETCH] = handle_fault_fetch,
     [CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction,
@@ -136,7 +136,6 @@ void handle_trap(trapframe_t* tf)
     [CAUSE_VECTOR_DISABLED] = handle_vector_disabled,
     [CAUSE_VECTOR_BANK] = handle_vector_bank,
     [CAUSE_VECTOR_ILLEGAL_INSTRUCTION] = handle_vector_illegal_instruction,
-    [CAUSE_IRQ0 + TIMER_IRQ] = handle_timer_interrupt,
   };
 
   kassert(tf->cause < ARRAY_SIZE(trap_handlers) && trap_handlers[tf->cause]);
diff --git a/pk/pcr.h b/pk/pcr.h
index c70b6c4..7659a97 100644
--- a/pk/pcr.h
+++ b/pk/pcr.h
@@ -1,18 +1,18 @@
-#ifndef _RISCV_COP0_H
-#define _RISCV_COP0_H
+#ifndef _RISCV_PCR_H
+#define _RISCV_PCR_H
 
-#define SR_ET    0x0000000000000001
-#define SR_EF    0x0000000000000002
-#define SR_EV    0x0000000000000004
-#define SR_EC    0x0000000000000008
-#define SR_PS    0x0000000000000010
-#define SR_S     0x0000000000000020
-#define SR_UX    0x0000000000000040
-#define SR_SX    0x0000000000000080
-#define SR_IM    0x000000000000FF00
-#define SR_VM    0x0000000000010000
-
-#define SR_IM_SHIFT 8
+#define SR_ET    0x00000001
+#define SR_EF    0x00000002
+#define SR_EV    0x00000004
+#define SR_EC    0x00000008
+#define SR_PS    0x00000010
+#define SR_S     0x00000020
+#define SR_U64   0x00000040
+#define SR_S64   0x00000080
+#define SR_VM    0x00000100
+#define SR_IM    0x00FF0000
+#define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
+#define SR_IM_SHIFT 16
 
 #define PCR_SR       0
 #define PCR_EPC      1
@@ -25,14 +25,17 @@
 #define PCR_SEND_IPI 8
 #define PCR_CLR_IPI  9
 #define PCR_COREID   10
+#define PCR_IMPL     11
 #define PCR_K0       12
 #define PCR_K1       13
-#define PCR_TOHOST   16
-#define PCR_FROMHOST 17
-#define PCR_CONSOLE  18
+#define PCR_VECBANK  18
+#define PCR_VECCFG   19
+#define PCR_RESET    29
+#define PCR_TOHOST   30
+#define PCR_FROMHOST 31
 
-#define IPI_IRQ   5
-#define TIMER_IRQ 7
+#define IRQ_IPI   5
+#define IRQ_TIMER 7
 
 #define CAUSE_MISALIGNED_FETCH 0
 #define CAUSE_FAULT_FETCH 1
@@ -47,31 +50,40 @@
 #define CAUSE_FAULT_STORE 11
 #define CAUSE_VECTOR_DISABLED 12
 #define CAUSE_VECTOR_BANK 13
-#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 14
-#define CAUSE_IRQ0 16
-#define CAUSE_IRQ1 17
-#define CAUSE_IRQ2 18
-#define CAUSE_IRQ3 19
-#define CAUSE_IRQ4 20
-#define CAUSE_IRQ5 21
-#define CAUSE_IRQ6 22
-#define CAUSE_IRQ7 23
-#define NUM_CAUSES 24
+
+#define CAUSE_VECTOR_MISALIGNED_FETCH 24
+#define CAUSE_VECTOR_FAULT_FETCH 25
+#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
+#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
+#define CAUSE_VECTOR_MISALIGNED_LOAD 28
+#define CAUSE_VECTOR_MISALIGNED_STORE 29
+#define CAUSE_VECTOR_FAULT_LOAD 30
+#define CAUSE_VECTOR_FAULT_STORE 31
+
+#ifdef __riscv
 
 #define ASM_CR(r)   _ASM_CR(r)
 #define _ASM_CR(r)  cr##r
 
 #ifndef __ASSEMBLER__
 
-#define mtpcr(reg,val) ({ long __tmp = (long)(val); \
-          asm volatile ("mtpcr %0,cr%1"::"r"(__tmp),"i"(reg)); })
+#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
+          asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
+          __tmp2; })
 
 #define mfpcr(reg) ({ long __tmp; \
           asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
           __tmp; })
 
-#define irq_disable() asm volatile("di")
-#define irq_enable() asm volatile("ei")
+#define setpcr(reg,val) ({ long __tmp; \
+          asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+          __tmp; })
+
+#define clearpcr(reg,val) ({ long __tmp; \
+          asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
+          __tmp; })
+
+#endif
 
 #endif
 
diff --git a/pk/pk.c b/pk/pk.c
index 33b0bda..2f516b9 100644
--- a/pk/pk.c
+++ b/pk/pk.c
@@ -127,9 +127,9 @@ void init_tf(trapframe_t* tf, long pc, long sp, int user64)
   memset(tf,0,sizeof(*tf));
   if(sizeof(void*) != 8)
     kassert(!user64);
-  tf->sr = (mfpcr(PCR_SR) & (SR_IM | SR_SX)) | SR_S | SR_EC;
+  tf->sr = (mfpcr(PCR_SR) & (SR_IM | SR_S64)) | SR_S | SR_EC;
   if(user64)
-    tf->sr |= SR_UX;
+    tf->sr |= SR_U64;
   tf->gpr[30] = sp;
   tf->epc = pc;
 }
diff --git a/pk/riscv-opc.h b/pk/riscv-opc.h
index c3d69ab..7bad495 100644
--- a/pk/riscv-opc.h
+++ b/pk/riscv-opc.h
@@ -50,7 +50,7 @@
 #define MATCH_FCVT_D_S 0x100d3
 #define  MASK_FCVT_D_S 0x3ff1ff
 #define MATCH_MFPCR 0x17b
-#define  MASK_MFPCR 0x7c1ffff
+#define  MASK_MFPCR 0x3fffff
 #define MATCH_C_FSD 0x18
 #define  MASK_C_FSD 0x1f
 #define MATCH_FMAX_D 0x190d3
@@ -69,14 +69,14 @@
 #define  MASK_VFLSTD 0x1ffff
 #define MATCH_C_LI 0x0
 #define  MASK_C_LI 0x1f
-#define MATCH_DI 0xfb
-#define  MASK_DI 0x7ffffff
+#define MATCH_FADD_D 0xd3
+#define  MASK_FADD_D 0x1f1ff
 #define MATCH_SLTIU 0x193
 #define  MASK_SLTIU 0x3ff
 #define MATCH_MTPCR 0x1fb
-#define  MASK_MTPCR 0xf801ffff
-#define MATCH_VXCPTWAIT 0x180fb
-#define  MASK_VXCPTWAIT 0xffffffff
+#define  MASK_MTPCR 0x1ffff
+#define MATCH_VLB 0xb
+#define  MASK_VLB 0x3fffff
 #define MATCH_STOP 0x177
 #define  MASK_STOP 0xffffffff
 #define MATCH_VLD 0x18b
@@ -95,7 +95,7 @@
 #define  MASK_MUL 0x1ffff
 #define MATCH_C_LW 0xa
 #define  MASK_C_LW 0x1f
-#define MATCH_VXCPTEVAC 0x1807b
+#define MATCH_VXCPTEVAC 0x237b
 #define  MASK_VXCPTEVAC 0xf83fffff
 #define MATCH_VLW 0x10b
 #define  MASK_VLW 0x3fffff
@@ -143,8 +143,6 @@
 #define  MASK_VVCFGIVL 0x3ff
 #define MATCH_J 0x67
 #define  MASK_J 0x7f
-#define MATCH_EI 0x7b
-#define  MASK_EI 0x7ffffff
 #define MATCH_FENCE 0x12f
 #define  MASK_FENCE 0x3ff
 #define MATCH_VSW 0x10f
@@ -175,8 +173,6 @@
 #define  MASK_FENCE_I 0x3ff
 #define MATCH_VLSEGBU 0x220b
 #define  MASK_VLSEGBU 0x1ffff
-#define MATCH_VLSEGSTB 0x80b
-#define  MASK_VLSEGSTB 0xfff
 #define MATCH_FNMSUB_D 0xcb
 #define  MASK_FNMSUB_D 0x1ff
 #define MATCH_ADDW 0x3b
@@ -257,20 +253,22 @@
 #define  MASK_VSSEGD 0x1ffff
 #define MATCH_SRL 0x2b3
 #define  MASK_SRL 0x1ffff
-#define MATCH_VENQCMD 0x181fb
+#define MATCH_VENQCMD 0x2b7b
 #define  MASK_VENQCMD 0xf801ffff
 #define MATCH_VFMTS 0x1973
 #define  MASK_VFMTS 0x1ffff
-#define MATCH_VENQIMM1 0x1827b
+#define MATCH_VENQIMM1 0x2f7b
 #define  MASK_VENQIMM1 0xf801ffff
 #define MATCH_FSGNJX_S 0x7053
 #define  MASK_FSGNJX_S 0x1ffff
 #define MATCH_VFMSV 0x973
 #define  MASK_VFMSV 0x3fffff
-#define MATCH_VENQIMM2 0x182fb
+#define MATCH_VENQIMM2 0x337b
 #define  MASK_VENQIMM2 0xf801ffff
 #define MATCH_FCVT_D_WU 0xf0d3
 #define  MASK_FCVT_D_WU 0x3ff1ff
+#define MATCH_VXCPTRESTORE 0x77b
+#define  MASK_VXCPTRESTORE 0xf83fffff
 #define MATCH_VMTS 0x1873
 #define  MASK_VMTS 0x1ffff
 #define MATCH_OR 0x333
@@ -315,7 +313,9 @@
 #define  MASK_RDTIME 0x7ffffff
 #define MATCH_ANDI 0x393
 #define  MASK_ANDI 0x3ff
-#define MATCH_VENQCNT 0x1837b
+#define MATCH_CLEARPCR 0x7b
+#define  MASK_CLEARPCR 0x3ff
+#define MATCH_VENQCNT 0x377b
 #define  MASK_VENQCNT 0xf801ffff
 #define MATCH_FSGNJN_D 0x60d3
 #define  MASK_FSGNJN_D 0x1ffff
@@ -435,9 +435,9 @@
 #define  MASK_C_SUB3 0x31f
 #define MATCH_VSH 0x8f
 #define  MASK_VSH 0x3fffff
-#define MATCH_VLB 0xb
-#define  MASK_VLB 0x3fffff
-#define MATCH_VXCPTSAVE 0x1007b
+#define MATCH_VLSEGSTB 0x80b
+#define  MASK_VLSEGSTB 0xfff
+#define MATCH_VXCPTSAVE 0x37b
 #define  MASK_VXCPTSAVE 0xf83fffff
 #define MATCH_VLSEGSTD 0x98b
 #define  MASK_VLSEGSTD 0xfff
@@ -461,13 +461,11 @@
 #define  MASK_VMSV 0x3fffff
 #define MATCH_VMST 0x1073
 #define  MASK_VMST 0x1ffff
-#define MATCH_FADD_D 0xd3
-#define  MASK_FADD_D 0x1f1ff
-#define MATCH_VXCPTRESTORE 0x100fb
-#define  MASK_VXCPTRESTORE 0xf83fffff
+#define MATCH_SETPCR 0xfb
+#define  MASK_SETPCR 0x3ff
 #define MATCH_RDNPC 0x26b
 #define  MASK_RDNPC 0x7ffffff
-#define MATCH_VXCPTHOLD 0x1817b
+#define MATCH_VXCPTHOLD 0x277b
 #define  MASK_VXCPTHOLD 0xffffffff
 #define MATCH_FCVT_S_L 0xc053
 #define  MASK_FCVT_S_L 0x3ff1ff
@@ -489,7 +487,7 @@
 #define  MASK_VSSEGH 0x1ffff
 #define MATCH_FSQRT_S 0x4053
 #define  MASK_FSQRT_S 0x3ff1ff
-#define MATCH_VXCPTKILL 0x1017b
+#define MATCH_VXCPTKILL 0xb7b
 #define  MASK_VXCPTKILL 0xffffffff
 #define MATCH_C_SRAI 0x1019
 #define  MASK_C_SRAI 0x1c1f
diff --git a/pk/riscv-pk.S b/pk/riscv-pk.S
index a27df82..f1fe216 100644
--- a/pk/riscv-pk.S
+++ b/pk/riscv-pk.S
@@ -13,7 +13,7 @@ _start:
   add t0, t0, %lo(trap_entry)
   mtpcr t0, ASM_CR(PCR_EVEC)
 
-  li t0, SR_S | SR_PS | SR_ET | SR_EC | SR_SX
+  li t0, SR_S | SR_PS | SR_ET | SR_EC | SR_S64
   or t1, t0, SR_EF | SR_EV
   mtpcr t1, ASM_CR(PCR_SR)
   mfpcr t1, ASM_CR(PCR_SR)