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author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-25 02:02:42 -0800 |
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committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-25 02:03:48 -0800 |
commit | f62e692e72d1626977be0e92f766bdeed305d903 (patch) | |
tree | 0823636782afa9a01505cb12a1f1c5c2909fcbf6 | |
parent | a8889d65d249a71f009433766a1e9b1405945708 (diff) | |
download | pk-f62e692e72d1626977be0e92f766bdeed305d903.zip pk-f62e692e72d1626977be0e92f766bdeed305d903.tar.gz pk-f62e692e72d1626977be0e92f766bdeed305d903.tar.bz2 |
Update to new privileged ISA
-rw-r--r-- | pk/device.c | 5 | ||||
-rw-r--r-- | pk/elf.c | 1 | ||||
-rw-r--r-- | pk/encoding.h | 626 | ||||
-rw-r--r-- | pk/entry.S | 40 | ||||
-rw-r--r-- | pk/file.c | 1 | ||||
-rw-r--r-- | pk/fp.c | 12 | ||||
-rw-r--r-- | pk/fp_asm.S | 2 | ||||
-rw-r--r-- | pk/frontend.c | 5 | ||||
-rw-r--r-- | pk/handlers.c | 5 | ||||
-rw-r--r-- | pk/init.c | 3 | ||||
-rw-r--r-- | pk/int.c | 2 | ||||
-rw-r--r-- | pk/pcr.h | 114 | ||||
-rw-r--r-- | pk/pk.S | 20 | ||||
-rw-r--r-- | pk/pk.h | 3 | ||||
-rw-r--r-- | pk/pk.mk.in | 3 | ||||
-rw-r--r-- | pk/riscv-opc.h | 317 | ||||
-rw-r--r-- | pk/syscall.c | 1 | ||||
-rw-r--r-- | pk/vm.c | 14 |
18 files changed, 674 insertions, 500 deletions
diff --git a/pk/device.c b/pk/device.c index aef59a1..73cd71d 100644 --- a/pk/device.c +++ b/pk/device.c @@ -1,5 +1,4 @@ #include "pk.h" -#include "pcr.h" #include <string.h> #include <stdlib.h> @@ -8,8 +7,8 @@ static uint64_t tohost_sync(unsigned dev, unsigned cmd, uint64_t payload) uint64_t tohost = (uint64_t)dev << 56 | (uint64_t)cmd << 48 | payload; uint64_t fromhost; __sync_synchronize(); - while (mtpcr(PCR_TOHOST, tohost)); - while ((fromhost = mtpcr(PCR_FROMHOST, 0)) == 0); + while (swap_csr(tohost, tohost) != 0); + while ((fromhost = swap_csr(fromhost, 0)) == 0); __sync_synchronize(); return fromhost; } @@ -2,7 +2,6 @@ #include "file.h" #include "pk.h" -#include "pcr.h" #include "vm.h" #include <sys/stat.h> #include <fcntl.h> diff --git a/pk/encoding.h b/pk/encoding.h new file mode 100644 index 0000000..92accfe --- /dev/null +++ b/pk/encoding.h @@ -0,0 +1,626 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define SR_S 0x00000001 +#define SR_PS 0x00000002 +#define SR_EI 0x00000004 +#define SR_PEI 0x00000008 +#define SR_EF 0x00000010 +#define SR_U64 0x00000020 +#define SR_S64 0x00000040 +#define SR_VM 0x00000080 +#define SR_EA 0x00000100 +#define SR_IM 0x00FF0000 +#define SR_IP 0xFF000000 +#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP) +#define SR_IM_SHIFT 16 +#define SR_IP_SHIFT 24 + +#define IRQ_COP 2 +#define IRQ_IPI 5 +#define IRQ_HOST 6 +#define IRQ_TIMER 7 + +#define IMPL_SPIKE 1 +#define IMPL_ROCKET 2 + +#define CAUSE_MISALIGNED_FETCH 0 +#define CAUSE_FAULT_FETCH 1 +#define CAUSE_ILLEGAL_INSTRUCTION 2 +#define CAUSE_PRIVILEGED_INSTRUCTION 3 +#define CAUSE_FP_DISABLED 4 +#define CAUSE_SYSCALL 6 +#define CAUSE_BREAKPOINT 7 +#define CAUSE_MISALIGNED_LOAD 8 +#define CAUSE_MISALIGNED_STORE 9 +#define CAUSE_FAULT_LOAD 10 +#define CAUSE_FAULT_STORE 11 +#define CAUSE_ACCELERATOR_DISABLED 12 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Entry is a page Table descriptor +#define PTE_T 0x002 // Entry is a page Table, not a terminal node +#define PTE_G 0x004 // Global +#define PTE_UR 0x008 // User Write permission +#define PTE_UW 0x010 // User Read permission +#define PTE_UX 0x020 // User eXecute permission +#define PTE_SR 0x040 // Supervisor Read permission +#define PTE_SW 0x080 // Supervisor Write permission +#define PTE_SX 0x100 // Supervisor eXecute permission +#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX) + +#ifdef __riscv + +#ifdef __riscv64 +# define RISCV_PGLEVELS 3 +# define RISCV_PGSHIFT 13 +#else +# define RISCV_PGLEVELS 2 +# define RISCV_PGSHIFT 12 +#endif +#define RISCV_PGLEVEL_BITS 10 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#define read_csr(reg) ({ long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)) + +#define swap_csr(reg, val) ({ long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ long __tmp; \ + if (__builtin_constant_p(bit) && (bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ long __tmp; \ + if (__builtin_constant_p(bit) && (bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdcycle() ({ unsigned long __tmp; \ + asm volatile ("rdcycle %0" : "=r"(__tmp)); \ + __tmp; }) + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_FMIN_D 0xc2000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_FSGNJN_D 0x32000053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FMIN_S 0xc0000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_FCVT_D_L 0x62000053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_FCVT_D_W 0x72000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_FMAX_D 0xca000053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_FCVT_S_D 0x88000053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FCVT_S_W 0x70000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_FCVT_S_LU 0x68000053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FCVT_L_S 0x40000053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_SBREAK 0x100073 +#define MASK_SBREAK 0xffffffff +#define MATCH_FLE_S 0xb8000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FLE_D 0xba000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_SCALL 0x73 +#define MASK_SCALL 0xffffffff +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_FLT_D 0xb2000053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_FLT_S 0xb0000053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_FEQ_S 0xa8000053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FSGNJX_D 0x3a000053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FSGNJX_S 0x38000053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FEQ_D 0xaa000053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_D_WU 0x7a000053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_FCVT_WU_D 0x5a000053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_FMAX_S 0xc8000053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_FCVT_WU_S 0x58000053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_SRET 0x80000073 +#define MASK_SRET 0xffffffff +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_JAL 0x67 +#define MASK_JAL 0x7f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCVT_D_S 0x82000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_FCVT_W_S 0x50000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_FCVT_D_LU 0x6a000053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_FCVT_W_D 0x52000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_FSGNJ_S 0x28000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_FSGNJ_D 0x2a000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_FCVT_L_D 0x42000053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_S_WU 0x78000053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_LU_S 0x48000053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FCVT_S_L 0x60000053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_FCVT_LU_D 0x4a000053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FSQRT_S 0x20000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_FSGNJN_S 0x30000053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_FSQRT_D 0x22000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_JALR 0x6f +#define MASK_JALR 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define CSR_SUP0 0x500 +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0x4 +#define CSR_TIME 0x5 +#define CSR_INSTRET 0x6 +#define CSR_SUP1 0x501 +#define CSR_EVEC 0x508 +#define CSR_CAUSE 0x509 +#define CSR_STATUS 0x50a +#define CSR_HARTID 0x50b +#define CSR_IMPL 0x50c +#define CSR_EPC 0x502 +#define CSR_SEND_IPI 0x50e +#define CSR_CLEAR_IPI 0x50f +#define CSR_BADVADDR 0x503 +#define CSR_PTBR 0x504 +#define CSR_STATS 0x51c +#define CSR_RESET 0x51d +#define CSR_TOHOST 0x51e +#define CSR_ASID 0x505 +#define CSR_COUNT 0x506 +#define CSR_COMPARE 0x507 +#define CSR_FROMHOST 0x51f +#define CSR_FATC 0x50d +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(sup0, CSR_SUP0) +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(sup1, CSR_SUP1) +DECLARE_CSR(evec, CSR_EVEC) +DECLARE_CSR(cause, CSR_CAUSE) +DECLARE_CSR(status, CSR_STATUS) +DECLARE_CSR(hartid, CSR_HARTID) +DECLARE_CSR(impl, CSR_IMPL) +DECLARE_CSR(epc, CSR_EPC) +DECLARE_CSR(send_ipi, CSR_SEND_IPI) +DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI) +DECLARE_CSR(badvaddr, CSR_BADVADDR) +DECLARE_CSR(ptbr, CSR_PTBR) +DECLARE_CSR(stats, CSR_STATS) +DECLARE_CSR(reset, CSR_RESET) +DECLARE_CSR(tohost, CSR_TOHOST) +DECLARE_CSR(asid, CSR_ASID) +DECLARE_CSR(count, CSR_COUNT) +DECLARE_CSR(compare, CSR_COMPARE) +DECLARE_CSR(fromhost, CSR_FROMHOST) +DECLARE_CSR(fatc, CSR_FATC) +#endif @@ -1,6 +1,6 @@ // See LICENSE for license details. -#include "pcr.h" +#include "encoding.h" #ifdef __riscv64 # define STORE sd @@ -46,12 +46,12 @@ # get sr, epc, badvaddr, cause - mfpcr x3,sup0 # x1 - mfpcr x4,sup1 # x2 - mfpcr x5,status - mfpcr x6,epc - mfpcr x7,badvaddr - mfpcr x8,cause + csrr x3,sup0 # x1 + csrr x4,sup1 # x2 + csrr x5,status + csrr x6,epc + csrr x7,badvaddr + csrr x8,cause STORE x3,1*REGBYTES(x2) STORE x4,2*REGBYTES(x2) STORE x5,32*REGBYTES(x2) @@ -73,9 +73,9 @@ pop_tf: # write the trap frame onto the stack LOAD a2,1*REGBYTES(a0) LOAD a3,2*REGBYTES(a0) - mtpcr a1,status # restore sr (disable interrupts) - mtpcr a2,sup0 - mtpcr a3,sup1 + csrw status, a1 # restore sr (disable interrupts) + csrw sup0, a2 + csrw sup1, a3 move x1,a0 LOAD x3,3*REGBYTES(x1) @@ -110,27 +110,27 @@ pop_tf: # write the trap frame onto the stack # gtfo! LOAD x2,33*REGBYTES(x1) - mfpcr x1,sup0 - mtpcr x2,epc - mfpcr x2,sup1 - eret + csrr x1, sup0 + csrw epc, x2 + csrr x2, sup1 + sret .global trap_entry trap_entry: - mtpcr x1,sup0 - mtpcr x2,sup1 + csrw sup0, x1 + csrw sup1, x2 # when coming from kernel, continue below its stack - mfpcr x1,status - and x1,x1,SR_PS + csrr x1, status + and x1, x1, SR_PS add x2, sp, -320 bnez x1, 1f - la x2,stack_top-320 + la x2, stack_top-320 1:save_tf move sp,x2 move a0,x2 - jal handle_trap + j handle_trap .bss .align 4 @@ -5,7 +5,6 @@ #include "file.h" #include "pk.h" #include "frontend.h" -#include "pcr.h" #include "vm.h" #define MAX_FDS 32 @@ -1,7 +1,6 @@ // See LICENSE for license details. #include "pk.h" -#include "pcr.h" #include "fp.h" #include "config.h" @@ -10,7 +9,6 @@ static fp_state_t fp_state; #ifdef PK_ENABLE_FP_EMULATION #include "softfloat.h" -#include "riscv-opc.h" #include <stdint.h> #define noisy 0 @@ -25,9 +23,9 @@ validate_address(trapframe_t* tf, long addr, int size, int store) int emulate_fp(trapframe_t* tf) { - if(have_fp) + if (have_fp) { - if(!(mfpcr(PCR_SR) & SR_EF)) + if (!(read_csr(status) & SR_EF)) init_fp(tf); fp_state.fsr = get_fp_state(fp_state.fpr); } @@ -263,10 +261,8 @@ get_fp_reg(unsigned int which, unsigned int dp) void init_fp(trapframe_t* tf) { - long sr = mfpcr(PCR_SR); - mtpcr(PCR_SR, sr | SR_EF); + tf->sr |= SR_EF; + set_csr(status, SR_EF); put_fp_state(fp_state.fpr,fp_state.fsr); - - tf->sr |= SR_EF; } diff --git a/pk/fp_asm.S b/pk/fp_asm.S index 37c4ef2..a247952 100644 --- a/pk/fp_asm.S +++ b/pk/fp_asm.S @@ -1,7 +1,5 @@ // See LICENSE for license details. -#include "pcr.h" - .text .globl get_fp_state get_fp_state: diff --git a/pk/frontend.c b/pk/frontend.c index 9614142..3452b23 100644 --- a/pk/frontend.c +++ b/pk/frontend.c @@ -3,7 +3,6 @@ #include "pk.h" #include "atomic.h" #include "frontend.h" -#include "pcr.h" #include <stdint.h> sysret_t frontend_syscall(long n, long a0, long a1, long a2, long a3) @@ -21,8 +20,8 @@ sysret_t frontend_syscall(long n, long a0, long a1, long a2, long a3) mb(); - mtpcr(PCR_TOHOST, magic_mem); - while (mtpcr(PCR_FROMHOST, 0) == 0); + write_csr(tohost, magic_mem); + while (swap_csr(fromhost, 0) == 0); mb(); diff --git a/pk/handlers.c b/pk/handlers.c index 8d71e4f..972a5dc 100644 --- a/pk/handlers.c +++ b/pk/handlers.c @@ -1,6 +1,5 @@ // See LICENSE for license details. -#include "pcr.h" #include "pk.h" #include "config.h" #include "syscall.h" @@ -55,7 +54,7 @@ static void handle_illegal_instruction(trapframe_t* tf) static void handle_fp_disabled(trapframe_t* tf) { - if(have_fp && !(mfpcr(PCR_SR) & SR_EF)) + if (have_fp && !(read_csr(status) & SR_EF)) init_fp(tf); else handle_illegal_instruction(tf); @@ -124,7 +123,7 @@ static void handle_syscall(trapframe_t* tf) void handle_trap(trapframe_t* tf) { - setpcr(PCR_SR, SR_EI); + set_csr(status, SR_EI); typedef void (*trap_handler)(trapframe_t*); @@ -1,6 +1,5 @@ // See LICENSE for license details. -#include "pcr.h" #include "pk.h" #include "file.h" #include "vm.h" @@ -16,7 +15,7 @@ void init_tf(trapframe_t* tf, long pc, long sp, int user64) memset(tf,0,sizeof(*tf)); if(sizeof(void*) != 8) kassert(!user64); - tf->sr = (mfpcr(PCR_SR) & (SR_IM | SR_S64 | SR_VM)) | SR_S | SR_PEI; + tf->sr = (read_csr(status) & (SR_IM | SR_S64 | SR_VM)) | SR_S | SR_PEI; if(user64) tf->sr |= SR_U64; tf->gpr[14] = sp; @@ -1,11 +1,9 @@ // See LICENSE for license details. #include "pk.h" -#include "pcr.h" #include "softint.h" -#include "riscv-opc.h" #include <stdint.h> #define noisy 0 diff --git a/pk/pcr.h b/pk/pcr.h deleted file mode 100644 index 6c6d986..0000000 --- a/pk/pcr.h +++ /dev/null @@ -1,114 +0,0 @@ -// See LICENSE for license details. - -#ifndef _RISCV_PCR_H -#define _RISCV_PCR_H - -#define SR_S 0x00000001 -#define SR_PS 0x00000002 -#define SR_EI 0x00000004 -#define SR_PEI 0x00000008 -#define SR_EF 0x00000010 -#define SR_U64 0x00000020 -#define SR_S64 0x00000040 -#define SR_VM 0x00000080 -#define SR_EA 0x00000100 -#define SR_IM 0x00FF0000 -#define SR_IP 0xFF000000 -#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP) -#define SR_IM_SHIFT 16 -#define SR_IP_SHIFT 24 - -#define PCR_SUP0 0 -#define PCR_SUP1 1 -#define PCR_EPC 2 -#define PCR_BADVADDR 3 -#define PCR_PTBR 4 -#define PCR_ASID 5 -#define PCR_COUNT 6 -#define PCR_COMPARE 7 -#define PCR_EVEC 8 -#define PCR_CAUSE 9 -#define PCR_SR 10 -#define PCR_HARTID 11 -#define PCR_IMPL 12 -#define PCR_FATC 13 -#define PCR_SEND_IPI 14 -#define PCR_CLR_IPI 15 -#define PCR_VECBANK 18 -#define PCR_VECCFG 19 -#define PCR_RESET 29 -#define PCR_TOHOST 30 -#define PCR_FROMHOST 31 - -#define IRQ_COP 2 -#define IRQ_IPI 5 -#define IRQ_HOST 6 -#define IRQ_TIMER 7 - -#define IMPL_SPIKE 1 -#define IMPL_ROCKET 2 - -#define CAUSE_MISALIGNED_FETCH 0 -#define CAUSE_FAULT_FETCH 1 -#define CAUSE_ILLEGAL_INSTRUCTION 2 -#define CAUSE_PRIVILEGED_INSTRUCTION 3 -#define CAUSE_FP_DISABLED 4 -#define CAUSE_SYSCALL 6 -#define CAUSE_BREAKPOINT 7 -#define CAUSE_MISALIGNED_LOAD 8 -#define CAUSE_MISALIGNED_STORE 9 -#define CAUSE_FAULT_LOAD 10 -#define CAUSE_FAULT_STORE 11 -#define CAUSE_ACCELERATOR_DISABLED 12 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Entry is a page Table descriptor -#define PTE_T 0x002 // Entry is a page Table, not a terminal node -#define PTE_G 0x004 // Global -#define PTE_UR 0x008 // User Write permission -#define PTE_UW 0x010 // User Read permission -#define PTE_UX 0x020 // User eXecute permission -#define PTE_SR 0x040 // Supervisor Read permission -#define PTE_SW 0x080 // Supervisor Write permission -#define PTE_SX 0x100 // Supervisor eXecute permission -#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX) - -#ifdef __riscv - -#ifdef __riscv64 -# define RISCV_PGLEVELS 3 -# define RISCV_PGSHIFT 13 -#else -# define RISCV_PGLEVELS 2 -# define RISCV_PGSHIFT 12 -#endif -#define RISCV_PGLEVEL_BITS 10 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \ - asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \ - __tmp2; }) - -#define mfpcr(reg) ({ long __tmp; \ - asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \ - __tmp; }) - -#define setpcr(reg,val) ({ long __tmp; \ - asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ - __tmp; }) - -#define clearpcr(reg,val) ({ long __tmp; \ - asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ - __tmp; }) - -#define rdcycle() ({ unsigned long __tmp; \ - asm volatile ("rdcycle %0" : "=r"(__tmp)); \ - __tmp; }) - -#endif - -#endif - -#endif @@ -1,24 +1,20 @@ // See LICENSE for license details. -#include "pcr.h" -#include "pk.h" +#include "encoding.h" .section .text,"ax",@progbits .globl _start _start: - lui sp, %hi(stack_top) - add sp, sp, %lo(stack_top) - - lui a0, %hi(trap_entry) - add a0, a0, %lo(trap_entry) - mtpcr a0, evec + la sp, stack_top + la a0, trap_entry + csrw evec, a0 li a0, SR_S | SR_PS | SR_EI | SR_S64 or a1, a0, SR_EF | SR_EA - mtpcr a1, status - mfpcr a1, status - mtpcr a0, status + csrw status, a1 + csrr a1, status + csrw status, a0 and a2, a1, SR_EF lui a0, %hi(have_fp) @@ -29,4 +25,4 @@ _start: sw a2, %lo(have_accelerator)(a0) lui a0, %hi(boot) - jalr a0, %lo(boot) + jr a0, %lo(boot) @@ -7,6 +7,7 @@ #include <stdint.h> #include <string.h> +#include "encoding.h" typedef struct { @@ -42,7 +43,7 @@ int emulate_int(trapframe_t*); void printk(const char* s, ...); void init_tf(trapframe_t*, long pc, long sp, int user64); -void pop_tf(trapframe_t*); +void pop_tf(trapframe_t*) __attribute__((noreturn)); void dump_tf(trapframe_t*); void unhandled_trap(trapframe_t*); diff --git a/pk/pk.mk.in b/pk/pk.mk.in index 14cc461..8b6733d 100644 --- a/pk/pk.mk.in +++ b/pk/pk.mk.in @@ -5,12 +5,11 @@ pk_subproject_deps = \ pk_hdrs = \ pk.h \ - pcr.h \ + encoding.h \ fp.h \ atomic.h \ file.h \ frontend.h \ - riscv-opc.h \ elf.h \ vm.h \ diff --git a/pk/riscv-opc.h b/pk/riscv-opc.h deleted file mode 100644 index 70b3cda..0000000 --- a/pk/riscv-opc.h +++ /dev/null @@ -1,317 +0,0 @@ -/* Automatically generated by parse-opcodes */ -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_FMIN_D 0xc2000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_FMIN_S 0xc0000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_FCVT_S_WU 0x78000053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_D_L 0x62000053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_FRSR 0xe8000053 -#define MASK_FRSR 0xfffff07f -#define MATCH_FCVT_D_W 0x72000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_FCVT_D_S 0x82000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_MFPCR 0x1073 -#define MASK_MFPCR 0xfff0707f -#define MATCH_FMAX_D 0xca000053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_RDCYCLE 0x4077 -#define MASK_RDCYCLE 0xfffff07f -#define MATCH_FCVT_S_D 0x88000053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_MTPCR 0x73 -#define MASK_MTPCR 0xfe00707f -#define MATCH_BREAK 0x1077 -#define MASK_BREAK 0xffffffff -#define MATCH_FCVT_S_W 0x70000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FCVT_L_S 0x40000053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FLE_S 0xb8000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FLE_D 0xba000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_ERET 0x4073 -#define MASK_ERET 0xffffffff -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_FCVT_S_LU 0x68000053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_FLT_D 0xb2000053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_FLT_S 0xb0000053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_FEQ_S 0xa8000053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FSGNJX_D 0x3a000053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FSGNJX_S 0x38000053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FEQ_D 0xaa000053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FCVT_D_WU 0x7a000053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_RDINSTRET 0x4004077 -#define MASK_RDINSTRET 0xfffff07f -#define MATCH_FCVT_WU_D 0x5a000053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_FMAX_S 0xc8000053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_FCVT_WU_S 0x58000053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_RDTIME 0x2004077 -#define MASK_RDTIME 0xfffff07f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_CLEARPCR 0x3073 -#define MASK_CLEARPCR 0x707f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_FSGNJN_D 0x32000053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_JAL 0x67 -#define MASK_JAL 0x7f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_FCVT_W_S 0x50000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_FCVT_D_LU 0x6a000053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_FCVT_W_D 0x52000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_SYSCALL 0x77 -#define MASK_SYSCALL 0xffffffff -#define MATCH_FSGNJ_S 0x28000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_FSGNJ_D 0x2a000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_FCVT_L_D 0x42000053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FSSR 0xf8000053 -#define MASK_FSSR 0xfff0707f -#define MATCH_SETPCR 0x2073 -#define MASK_SETPCR 0x707f -#define MATCH_FCVT_LU_S 0x48000053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FCVT_S_L 0x60000053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_FCVT_LU_D 0x4a000053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FSQRT_S 0x20000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_FSGNJN_S 0x30000053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_FSQRT_D 0x22000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_JALR 0x6f -#define MASK_JALR 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f diff --git a/pk/syscall.c b/pk/syscall.c index 4180eb2..a4785a6 100644 --- a/pk/syscall.c +++ b/pk/syscall.c @@ -2,7 +2,6 @@ #include "syscall.h" #include "pk.h" -#include "pcr.h" #include "file.h" #include "frontend.h" #include "vm.h" @@ -1,7 +1,6 @@ #include "vm.h" #include "file.h" #include "atomic.h" -#include "pcr.h" #include "pk.h" #include <stdint.h> #include <errno.h> @@ -156,7 +155,7 @@ static uintptr_t __vm_alloc(size_t npage) static void flush_tlb() { - mtpcr(PCR_FATC, 0); + write_csr(fatc, 0); } static int __handle_page_fault(uintptr_t vaddr, int prot) @@ -397,7 +396,7 @@ void vm_init() size_t mem_pages = max_addr >> RISCV_PGSHIFT; const size_t min_free_pages = 2*RISCV_PGLEVELS; const size_t min_stack_pages = 8; - const size_t max_stack_pages = 128; + const size_t max_stack_pages = 1024; kassert(mem_pages > min_free_pages + min_stack_pages); free_pages = MAX(mem_pages >> (RISCV_PGLEVEL_BITS-1), min_free_pages); size_t stack_pages = CLAMP(mem_pages/32, min_stack_pages, max_stack_pages); @@ -409,10 +408,9 @@ void vm_init() __map_kernel_range(0, current.user_min, PROT_READ|PROT_WRITE|PROT_EXEC); - mtpcr(PCR_PTBR, root_page_table_paddr); - setpcr(PCR_SR, SR_VM); - have_vm = mfpcr(PCR_SR) & SR_VM; - clearpcr(PCR_SR, SR_VM); + write_csr(ptbr, root_page_table_paddr); + set_csr(status, SR_VM); + have_vm = clear_csr(status, SR_VM) & SR_VM; size_t stack_size = RISCV_PGSIZE * stack_pages; current.stack_top = MIN(first_free_page, 0x80000000); // for RV32 sanity @@ -422,7 +420,7 @@ void vm_init() { __map_kernel_range(first_free_page, free_pages * RISCV_PGSIZE, PROT_READ|PROT_WRITE); kassert(__do_mmap(stack_bot, stack_size, -1, MAP_FIXED|MAP_PRIVATE|MAP_ANONYMOUS, 0, 0) == stack_bot); - setpcr(PCR_SR, SR_VM); + set_csr(status, SR_VM); } current.stack_bottom = stack_bot; |