From 69f8cb36d3fa68fc514d26af77576fab838da625 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 9 Aug 2011 15:20:03 +0000 Subject: gas/ * config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret". --- include/opcode/ChangeLog | 10 ++++++++++ include/opcode/mips.h | 28 +++++++++++++++++++++++----- 2 files changed, 33 insertions(+), 5 deletions(-) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 4d88f24..a69f746 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,13 @@ +2011-08-09 Chao-ying Fu + Maciej W. Rozycki + + * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. + (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. + (INSN_ASE_MASK): Add the MCU bit. + (INSN_MCU): New macro. + (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. + (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. + 2011-08-09 Maciej W. Rozycki * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 1db4aed..e6703f8 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -187,6 +187,12 @@ #define OP_SH_MTACC_D 13 #define OP_MASK_MTACC_D 0x3 +/* MIPS MCU ASE */ +#define OP_MASK_3BITPOS 0x7 +#define OP_SH_3BITPOS 12 +#define OP_MASK_OFFSET12 0xfff +#define OP_SH_OFFSET12 0 + #define OP_OP_COP0 0x10 #define OP_OP_COP1 0x11 #define OP_OP_COP2 0x12 @@ -251,8 +257,6 @@ #define OP_SH_CODE10 0 #define OP_MASK_TRAP 0 #define OP_SH_TRAP 0 -#define OP_MASK_OFFSET12 0 -#define OP_SH_OFFSET12 0 #define OP_MASK_OFFSET10 0 #define OP_SH_OFFSET10 0 #define OP_MASK_RS3 0 @@ -473,6 +477,10 @@ struct mips_opcode "+t" 5 bit coprocessor 0 destination register (OP_*_RT) "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only + MCU ASE usage: + "~" 12 bit offset (OP_*_OFFSET12) + "\" 3 bit position for aset and aclr (OP_*_3BITPOS) + UDI immediates: "+1" UDI immediate bits 6-10 "+2" UDI immediate bits 6-15 @@ -508,7 +516,7 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "1234567890" - "%[]<>(),+:'@!$*&" + "%[]<>(),+:'@!$*&\~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxz" @@ -711,7 +719,7 @@ static const unsigned int mips_isa_table[] = #define INSN_OCTEON 0x00000800 /* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x3c00f000 +#define INSN_ASE_MASK 0x3c00f010 /* DSP ASE */ #define INSN_DSP 0x00001000 @@ -760,6 +768,9 @@ static const unsigned int mips_isa_table[] = /* RMI Xlr instruction */ #define INSN_XLR 0x00000020 +/* MCU (MicroController) ASE */ +#define INSN_MCU 0x00000010 + /* MIPS ISA defines, use instead of hardcoding ISA level. */ #define ISA_UNKNOWN 0 /* Gas internal use. */ @@ -862,9 +873,13 @@ static const unsigned int mips_isa_table[] = enum { M_ABS, + M_ACLR_AB, + M_ACLR_OB, M_ADD_I, M_ADDU_I, M_AND_I, + M_ASET_AB, + M_ASET_OB, M_BALIGN, M_BC1FL, M_BC1TL, @@ -1366,6 +1381,8 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_SEL 11 #define MICROMIPSOP_MASK_OFFSET12 0xfff #define MICROMIPSOP_SH_OFFSET12 0 +#define MICROMIPSOP_MASK_3BITPOS 0x7 +#define MICROMIPSOP_SH_3BITPOS 21 #define MICROMIPSOP_MASK_STYPE 0x1f #define MICROMIPSOP_SH_STYPE 16 #define MICROMIPSOP_MASK_OFFSET10 0x3ff @@ -1591,6 +1608,7 @@ extern const int bfd_mips16_num_opcodes; "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) ">" shift amount between 32 and 63, stored after subtracting 32 (MICROMIPSOP_*_SHAMT) + "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) "|" 4-bit trap code (MICROMIPSOP_*_TRAP) "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) "a" 26-bit target address (MICROMIPSOP_*_TARGET) @@ -1680,7 +1698,7 @@ extern const int bfd_mips16_num_opcodes; Characters used so far, for quick reference when adding more: "1234567890" - "<>(),+.|~" + "<>(),+.\|~" "ABCDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" -- cgit v1.1