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Initialize the jli_base registers for ARCv2 cpus.
libgloss/
2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc/crt0.S: Initialize the jli_base registers for ARCv2 cpus.
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Add profile support for ARC processors.
libgloss/
2016-07-28 Claudiu Zissulescu <claziss@synopsys.com>
* arc/crt0.S: Add calls to profiler support routines.
* Makefile.in (CRT0): Add gcrt0.
(NSIM_OBJS): Add mcount.
(CRT0_INSTALL): Install gcrt0, and crt0.
* arc/gcrt0.S: New file.
* arc/mcount.c: Likewise.
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libgloss/
2016-06-28 Claudiu Zissulescu <claziss@synopsys.com>
* arc/crt0.S: Add align keyword.
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ARCompact processors (ARC 600 and ARC 700) require three "nop"s after the
"flag 1" instruction. Later ARC processors do not have this requirement, so
it is possible to reduce size of "_exit_halt" for them.
libgloss/
2016-05-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc/crt0.S (_exit_halt): Insert nops only for ARCompact.
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Initially crt0.S used a special function, declared as weak as a default
exception handler in interrupt vector table. To let user override individual
handlers, this function had multiple names - one for each IVT entry, which,
however, was terribly confusing for the debugger and user - because it
wasn't clear which symbol will be used as a function name in debugger.
Defining multiple separate functions - one for each handler, would resolve
the mess, but would increase code size of crt0.o.
To clean this up, this patch defines exception handlers as weak symbols as
well, but those are defined as just symbols, not functions, hence there
would be less confusion over what is what. At the same time, users still can
redefine exception handlers symbol by creating functions with respective
names.
libgloss/
2016-05-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc/crt0.S: Convert memory_error and friends to non-function
symbols.
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crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.
Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.
libgloss/ChangeLog
2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com>
* arc/crt0.S: Fix support for processors without barrel-shifter.
Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
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This is similar to commit 06537f05d4b6a0d2db01c6afda1d2a0ea2588126 to the
newlib for ARC.
GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:
* __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
-mbarrel-shifter
* __ARCEM__ instead of __EM__ for ARC EM cores
* __ARCHS__ instead of __HS__ for ARC HS cores
* etc (not used in libgloss)
This patch updates crt0.S for ARC to use new definitions instead of a
deprecated ones. To ensure compatibility with older compiler new definitions
are also defined in crt0.S if needed, based on presence of deprecated
preprocessor definitions.
libgloss/ChangeLog
2016-04-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc/crt0.S: Use new GCC defines to detect processor features.
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ARC aproach to this feature is similiar to ARM's one here.
2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com>
* arc/nano.specs: New file.
* arc/Makefile.in: Support nano.specs.
* arc/nsim.specs: Likewise.
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ChangeLog:
2015-11-12 Anton Kolesov <Anton.Kolesov@synopsys.com>
* configure.in: Add ARC support to libgloss.
* configure: Regenerate.
libgloss/ChangeLog:
2015-11-12 Anton Kolesov <Anton.Kolesov@synopsys.com>
* configure: Add ARC support.
* configure.in: Likewise.
* arc/Makefile.in: Likewise.
* arc/aclocal.m4: Likewise.
* arc/configure: Likewise.
* arc/configure.in: Likewise.
* arc/crt0.S: Likewise.
* arc/libcfunc.c: Likewise.
* arc/nsim-syscall.h: Likewise.
* arc/nsim-syscalls.c: Likewise.
* arc/nsim.specs: Likewise.
* arc/sbrk.c: Likewise.
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