newlib: add Xtensa port

12 files changed, 503 insertions, 0 deletions

diff --git a/newlib/libm/machine/xtensa/Makefile.inc b/newlib/libm/machine/xtensa/Makefile.inc
new file mode 100644
index 0000000..3c95a56
--- /dev/null
+++ b/newlib/libm/machine/xtensa/Makefile.inc
@@ -0,0 +1,12 @@
+%C%_src = \
+	%D%/feclearexcept.c %D%/fegetenv.c %D%/fegetexcept.c %D%/fegetexceptflag.c \
+	%D%/fegetround.c %D%/feholdexcept.c %D%/feraiseexcept.c %D%/fetestexcept.c \
+	%D%/feupdateenv.c
+
+if XTENSA_XCHAL_HAVE_FP_SQRT
+%C%_src += \
+	%D%/ef_sqrt.c
+endif
+
+libm_a_CFLAGS_%C% = -D_LIBM
+libm_a_SOURCES += $(%C%_src)
diff --git a/newlib/libm/machine/xtensa/acinclude.m4 b/newlib/libm/machine/xtensa/acinclude.m4
new file mode 100644
index 0000000..4d242e0
--- /dev/null
+++ b/newlib/libm/machine/xtensa/acinclude.m4
@@ -0,0 +1,11 @@
+AC_CACHE_CHECK([for XCHAL_HAVE_FP_SQRT], newlib_cv_xchal_have_fp_sqrt, [dnl
+    AC_PREPROC_IFELSE([AC_LANG_PROGRAM(
+[[#define _LIBM
+// targ-include does not exist yet, use relative path
+#include "../sys/xtensa/include/xtensa/config/core-isa.h"
+#if (!XCHAL_HAVE_FP_SQRT)
+# error "Have not XCHAL_HAVE_FP_SQRT"
+#endif
+]])], [newlib_cv_xchal_have_fp_sqrt="yes"], [newlib_cv_xchal_have_fp_sqrt="no"])])
+
+AM_CONDITIONAL(XTENSA_XCHAL_HAVE_FP_SQRT, test "$newlib_cv_xchal_have_fp_sqrt" = "yes")
diff --git a/newlib/libm/machine/xtensa/ef_sqrt.c b/newlib/libm/machine/xtensa/ef_sqrt.c
new file mode 100644
index 0000000..39e8d75
--- /dev/null
+++ b/newlib/libm/machine/xtensa/ef_sqrt.c
@@ -0,0 +1,7 @@
+#include <xtensa/config/core-isa.h>
+
+#if !XCHAL_HAVE_FP_SQRT
+#error "__ieee754_sqrtf from common libm must be used"
+#else
+/* Built-in GCC __ieee754_sqrtf must be used */
+#endif
diff --git a/newlib/libm/machine/xtensa/feclearexcept.c b/newlib/libm/machine/xtensa/feclearexcept.c
new file mode 100644
index 0000000..f1bd84f
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feclearexcept.c
@@ -0,0 +1,48 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+
+int feclearexcept(int except)
+{
+  unsigned int fsr;
+
+  if (except & ~FE_ALL_EXCEPT)
+    return -1;
+  except <<= _FE_EXCEPTION_FLAGS_OFFSET;
+  asm ("rur.fsr %0" : "=a"(fsr));
+  fsr = fsr & ~except;
+  asm ("wur.fsr %0" : : "a"(fsr));
+  return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetenv.c b/newlib/libm/machine/xtensa/fegetenv.c
new file mode 100644
index 0000000..b3984ee
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetenv.c
@@ -0,0 +1,55 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fegetenv(fenv_t * env_ptr)
+{
+  unsigned int fsr;
+  unsigned int fcr;
+  asm ("rur.fsr %0" : "=a"(fsr));
+  asm ("rur.fcr %0" : "=a"(fcr));
+  *env_ptr = fsr | fcr;
+  return 0;
+}
+
+
+int fesetenv(const fenv_t * env_ptr)
+{
+  fenv_t env = *env_ptr;
+  if (env & ~(_FE_FLOATING_ENV_MASK))
+    return -1;
+  asm ("wur.fsr %0" : : "a"(*env_ptr));
+  asm ("wur.fcr %0" : : "a"(*env_ptr));
+  return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetexcept.c b/newlib/libm/machine/xtensa/fegetexcept.c
new file mode 100644
index 0000000..250917c
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetexcept.c
@@ -0,0 +1,67 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+/* These functions are glibc extensions.  */
+
+#include <fenv.h>
+
+int fegetexcept(void)
+{
+  fexcept_t current;
+  asm ("rur.fsr %0" : "=a"(current));
+  return (current >> _FE_EXCEPTION_ENABLE_OFFSET) & FE_ALL_EXCEPT;
+}
+
+
+int feenableexcept(int excepts)
+{
+  fexcept_t current;
+  if (excepts & ~FE_ALL_EXCEPT)
+    return -1;
+  asm ("rur.fcr %0" : "=a"(current));
+  current |= excepts << _FE_EXCEPTION_ENABLE_OFFSET;
+  asm ("wur.fcr %0" : "=a"(current));
+  return 0;
+}
+
+
+int fedisableexcept(int excepts)
+{
+  fexcept_t current;
+  if (excepts & ~FE_ALL_EXCEPT)
+    return -1;
+  asm ("rur.fcr %0" : "=a"(current));
+  current &= ~(excepts << _FE_EXCEPTION_ENABLE_OFFSET);
+  asm ("wur.fcr %0" : "=a"(current));
+  return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetexceptflag.c b/newlib/libm/machine/xtensa/fegetexceptflag.c
new file mode 100644
index 0000000..6d9e7e6
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetexceptflag.c
@@ -0,0 +1,63 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fegetexceptflag(fexcept_t *flagp, int excepts)
+{
+  unsigned int fsr;
+  if (excepts & ~FE_ALL_EXCEPT)
+    return -1;
+  asm ("rur.fsr %0" : "=a"(fsr));
+  fsr >>= _FE_EXCEPTION_FLAGS_OFFSET;
+  excepts &= fsr;
+  *flagp = excepts;
+
+  return 0;
+}
+
+
+int fesetexceptflag(const fexcept_t *flagp, int excepts)
+{
+  if (excepts & ~FE_ALL_EXCEPT)
+    return -1;
+
+  unsigned int fsr;
+
+  asm ("rur.fsr %0" : "=a"(fsr));
+
+  fsr &= ~(excepts << _FE_EXCEPTION_FLAGS_OFFSET);
+  fsr |= ((*flagp & excepts) << _FE_EXCEPTION_FLAGS_OFFSET);
+  asm ("wur.fsr %0" : : "a"(fsr));
+  return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetround.c b/newlib/libm/machine/xtensa/fegetround.c
new file mode 100644
index 0000000..f17be6d
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetround.c
@@ -0,0 +1,50 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fegetround(void)
+{
+  fexcept_t current;
+  asm ("rur.fcr %0" : "=a"(current));
+  return (current & _FE_ROUND_MODE_MASK) >> _FE_ROUND_MODE_OFFSET;
+}
+
+
+int fesetround(int round)
+{
+  if (round & ~_FE_ROUND_MODE_MASK)
+    return -1;
+  asm ("wur.fcr %0" : : "a"(round));
+  return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/feholdexcept.c b/newlib/libm/machine/xtensa/feholdexcept.c
new file mode 100644
index 0000000..32e5e0b
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feholdexcept.c
@@ -0,0 +1,54 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int feholdexcept(fenv_t * envp)
+{
+  fexcept_t fsr;
+  fenv_t fcr;
+  /* Get the environment.  */
+  asm ("rur.fcr %0" : "=a"(fcr));
+  asm ("rur.fsr %0" : "=a"(fsr));
+  *envp = fsr | fcr;
+
+  /* Clear the exception enable flags.  */
+  fcr &= _FE_ROUND_MODE_MASK;
+  asm ("wur.fcr %0" : :"a"(fcr));
+
+  /* Clear the exception happened flags.  */
+  fsr = 0;
+  asm ("wur.fsr %0" : :"a"(fsr));
+
+  return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/feraiseexcept.c b/newlib/libm/machine/xtensa/feraiseexcept.c
new file mode 100644
index 0000000..8d418f0
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feraiseexcept.c
@@ -0,0 +1,49 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+/* Xtensa doesn't trap, so setting the flags is the best we can
+   do.  */
+
+#include <fenv.h>
+
+int feraiseexcept(int excepts)
+{
+  fexcept_t current;
+
+  if (excepts & ~FE_ALL_EXCEPT)
+    return -1;
+  asm ("rur.fsr %0" : "=a"(current));
+  current |= excepts << _FE_EXCEPTION_FLAGS_OFFSET;
+  asm ("wur.fsr %0" : : "a"(current));
+  return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fetestexcept.c b/newlib/libm/machine/xtensa/fetestexcept.c
new file mode 100644
index 0000000..2950859
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fetestexcept.c
@@ -0,0 +1,41 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fetestexcept(int excepts)
+{
+  fexcept_t current;
+  asm ("rur.fsr %0" : "=a"(current));
+  return (current >> _FE_EXCEPTION_FLAGS_OFFSET) & excepts;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/feupdateenv.c b/newlib/libm/machine/xtensa/feupdateenv.c
new file mode 100644
index 0000000..cbb1ffa
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feupdateenv.c
@@ -0,0 +1,46 @@
+/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials provided
+      with the distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int feupdateenv(const fenv_t * envp)
+{
+  fenv_t current;
+  int err = fegetenv (&current);
+  if (err != 0)
+    return err;
+  err = fesetenv (envp);
+  if (err != 0)
+    return err;
+  return feraiseexcept (current);
+}
+
+#endif