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authorTamar Christina <tamar.christina@arm.com>2019-02-08 17:13:24 +0000
committerCorinna Vinschen <corinna@vinschen.de>2019-02-11 12:49:23 +0100
commit1ba66fe8fa94b2148c12beae9948b0cdf6bf1ffa (patch)
tree2fc6ebba5fe902c0d79982edd2ebab7bbb6db4e5 /libgloss/arm
parent52d91f112ec2e5dd62edd200ca547bb11e52effa (diff)
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AArch32: Fix the build for M class semihosting
The M class cores don't support Semihosting v2 mixed mode, but we were accidentally using the new immediates for it. My last patch changed the immediates which broke the build because doing a full multi-lib build including M architectures now results in an assembler error instead of silently doing the wrong thing. This fixes the issue by changing the defines around such that According to the specs any M class build uses the normal semihosting instructions. Regtested on arm-none-eabi and no issues, using a build with m class multilibs too.
Diffstat (limited to 'libgloss/arm')
-rw-r--r--libgloss/arm/swi.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/libgloss/arm/swi.h b/libgloss/arm/swi.h
index 8f50ee7..267d164 100644
--- a/libgloss/arm/swi.h
+++ b/libgloss/arm/swi.h
@@ -30,7 +30,9 @@
/* Now the SWI numbers and reason codes for RDI (Angel) monitors. */
-#if defined (SEMIHOST_V2) && defined (SEMIHOST_V2_MIXED_MODE)
+#if defined (SEMIHOST_V2) \
+ && defined (SEMIHOST_V2_MIXED_MODE) \
+ && !defined (THUMB_VXM)
#define AngelSWI_ARM 0xE10F0070 /* HLT #0xF000 A32. */
#ifdef __thumb__
#define AngelSWI 0xBABC /* HLT #0x3c T32. */